Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
memory in spartan 3 fpga
Hi, I'd like to set up block rams(16k) to acts as a ROM lookup table after initialization. After establishing the Memory Area as an FPGA resource there's an option to initialize it by using memory...
2
|
16 years ago
|
2 | |
|
|
intialize memory in fpga
I'd like to set up block rams(16k) to acts as a ROM lookup table after initialization. After establishing the Memory Area as an FPGA resource there's an option to initialize it by using memory eritor....
3
|
16 years ago
|
3 | |
|
|
Question about xflow?
Hi, Now, I learn xflow of xilinx. I want to generate a function simulation output file. For the example vhdl file: watchvhd, according to the Development System Reference Guid, I use the command:...
1
|
16 years ago
|
1 | |
|
|
Strange behaviour of a design
I am working now for some days on a strange behaviour of a fpga. The design is complete synchron. I have the problem that when I change in a state machine a signal, then the design doesn't function...
9
|
16 years ago
|
9 | |
|
|
VHDL core to read/write to Bram_Block.
Hi, I have implemented a core to write/read to a Bram_Block (using one of the two ports). The another port is used by Microblaze with a lmb_bram_if_cntlr core to read those values which had been...
3
|
16 years ago
|
3 | |
|
|
altera's USB byteblaster cable: anyone has the mindford one?
Hi all, I haven't used any altera stuff for a while. Last time I used the MAX3000A, I built the parallel port byteblaster cable from the info on the altera's web site. This is the original not the...
2
|
16 years ago
|
2 | |
|
|
Problems with PLB_DDR2 core and soft reset
I'm developing an embedded PPC405 system on a Xilinx FPGA and Im hoping I can get some insight on this problem. I'm using the PLB_DDR2 xilinx ip core to interface two DDR2 memory. Currently I can...
4
|
16 years ago
|
4 | |
|
|
VGA controller in the EDK ?
Could some kind soul please tell me if there's a Xilinx-supplied VGA controller in the EDK ? Looking on 't mention one, but I've come across mentions of one while searching Usenet... All very...
4
|
16 years ago
|
4 | |
|
|
PCB Layers
Hi I am designing a pcb with a Virtex 4 FX in a FF672 package. Is there general rule of how many layers the pcb will need to route out all th pins? Cheers Jon
19
|
16 years ago
|
19 | |
|
|
Xilinx Virtex IOB Regiters and Noise???
I am registering a data bus at the input of a Xilinx Virtex FPGA (XCV300) using IOB registers. It appears that some of the register bits are locking in incorrect data. All registered bits are brought...
4
|
16 years ago
|
4 | |
|
|
VHDL clocking scheme VS Verilog clocking scheme
Hi, I am confused about the clocking scheme of the two most popular hdl. The most common usage of clock and reset signal is clk'event clk=3D1 or reset=3D1. As you see reset signal seem to be a level...
3
|
16 years ago
|
3 | |
|
|
XHWIF interface for Virtex II devices
Hi, I was wondering if anyone has implemented the XHWIF interface for any Virtex II device in other words the C/C++ dlls required to make the interface work I was planning write the source on my own...
—
|
16 years ago
|
— | |
|
|
weird issue on Xilinx ML501/ML505 evkit designs
Hi, Usually I do not post such questions but I've got no answer from Xilinx and I want to be sure I have right. I've took a deep look to the SODIMM schematic side of ML501 and ML505 from Xilinx. See...
—
|
16 years ago
|
— | |
|
|
New keyword 'orif' and its implications
Hi, I open a new topics from previous one to try to stir another round to introduce a new keyword 'orif'. Hi Andy, A group of signals is defined as mutually exclusive if either no signal or only one...
64
|
16 years ago
|
64 | |
|
|
PLL Power and m/n ratio
Hi Folks, I am wondering the implications on PLL power compared to the m/n ratio that is used to generate a particular frequency. So which consumes more power? a. 25MHz src clock into the PLL that...
6
|
16 years ago
|
6 |