VHDL clocking scheme VS Verilog clocking scheme


I am confused about the clocking scheme of the two most popular hdl. The most common usage of clock and reset signal is clk'event clk=3D1 or reset=3D1. As you see reset signal seem to be a level sensitive as it should be. But in verilog the common structure for clocking is posedge clk or negedge reset. As you see there is an edge constraint for reset signal in verilog. Why this is different in these hdls. Does this have any importance from the technology point of view ? I mean if the synthesized circuits are same or different by the same synthesis tool.


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I hope you are now using the much clearer form rising_edge(clock) but yes, you're right.

Because Verilog cannot detect the clock edge in procedural code.

Many people are surprised to see the edge specification on reset in Verilog. However, think what would happen without it....

always @((posedge clock) or reset) /// WRONG if (reset == 1'b0) Q any importance from the technology point of view ? I mean if the

No. Synthesis treats the standard clocked templates in the same way for Verilog and VHDL.

The one big difference is that it is effectively impossible to use this style in Verilog to describe a flip-flop that has BOTH asynchronous set AND asynchronous reset, whereas in VHDL it's easy. In practice, though, this isn't a significant problem.

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Jonathan Bromley

The big difference between the Verilog and VHDL template is the lack of an "if" along with the "else". In the case of clock frozen at 0, you might be able to fix this using else if (clock) but then you'd have bad behavior in the clock frozen high case.

In non-synthesizable code you could add @(posedge clock) in the else clause, but that would require waiting for an additional clock edge when the always block is triggered by the rising edge of clock.

What about?

always @(posedge clock or negedge reset_n or negedge set_n) if (!reset_n) Q

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Jonathan Bromley

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