I am confused about the clocking scheme of the two most popular hdl. The most common usage of clock and reset signal is clk'event clk=3D1 or reset=3D1. As you see reset signal seem to be a level sensitive as it should be. But in verilog the common structure for clocking is posedge clk or negedge reset. As you see there is an edge constraint for reset signal in verilog. Why this is different in these hdls. Does this have any importance from the technology point of view ? I mean if the synthesized circuits are same or different by the same synthesis tool.