PLL Power and m/n ratio

Hi Folks,

I am wondering the implications on PLL power compared to the m/n ratio that is used to generate a particular frequency. So which consumes more power?

a. 25MHz src clock into the PLL that generates a 200MHz clock b. 100MHz src clock, 200MHz synthesized clock

Thank you. Best regards, Sanjay

Reply to
fpgabuilder
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Sanjay,

I suggest you use the power estimator spreadsheet to answer your question.

You did not say if you were asking about Xilinx, or someone else. You will find the V5 power estimator here:

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Austin

Reply to
austin

Either way, I suspect the input frequency has less to do with power consumption than the VCO frequency. The latter is generally only a function of the output divisor.

Reply to
Gabor

Hello Sanjay,

Our experience is that the PLL's power consumption is fairly low as compared to the clock network it is driving in most cases. To get a sense for the amount of power the PLL consumes as a function of the VCO frequency, download a copy of the Early Power Estimator spreadsheet for the device you are interested in

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For a more detailed analysis, grab a copy of Quartus and fire up a toy design with the PLL in it, and run it through the PowerPlay Power Analyser. The PLL models for 90 nm and 65 nm devices take into account your VCO frequency, M/N values, and counter settings.

Regards,

Paul Leventis Altera Corp.

Reply to
Paul Leventis

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I tried to use the Altera spreadsheet for Stratix3 device as that is what I am targetting at present. It seems like the PLL power requirement changes only with the VCO frequency. But I am guessing this does not say much as the VCO frequency will change depending upon the input frequency assuming output frequency is kept the same.

Reply to
fpgabuilder

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I think you mean to say "will _not_ change ... assuming output frequency is kept the same"?

Normally the VCO frequency is the desired output frequency multiplied by the required output divider. Since your two input frequencies are related (4:1) I would not expect you to change the output divider, and therefore to end up with the same VCO frequency and (roughly) the same power usage in either case.

Regards, Gabor

Reply to
Gabor

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I guess that makes sense in this case because to generate the output frequency we only need to divide the vco frequency. If the input frequency would be required to be multiplied before the vco frequency can be divided, I would think the power consumed would change. Maybe I didn't think through this...

Reply to
fpgabuilder

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