Problems with PLB_DDR2 core and soft reset

Just asking: the DDR2 memories are properly routed ? What kind of terminators are onboard? If active terminators used are they programmed correctly in the FPGA ? Probably through the jtag the W/R sequence to DDR2 is slower and everything it's ok.

Ah, I think i said that in a confusing way. The processor is executing instructions (reading/writing to DDR2 using the plb_ddr2 core), im just loading instructions to the proc via the jtag chain with XMD debug command prompt instead of loading code into block ram. So I'm fairly confident that the hardware is correct (or at least correct enough to write reliably to the DDR2 BEFORE a soft system reset.

Also, some info i may not have given initially: Im using the xilinx reset module typically instantiated with EDK. It's driving my plb and opb bus resets. As far as i can tell, the plb reset is the only reset signal going to the plb_ddr2 core.

Could the reset signal not be the proper length/format for the DDR controller? I just mention this because I had a DSOCM design where using the sys_rst_s signal didn't work, but did when I switched it to sys_bus_reset.

Ok, I think I found a fix. Setting the "autocalibration" option to false on both of my DCMs to the DDR2 core seems to have solved the problem. ( See this post: