I'm developing an embedded PPC405 system on a Xilinx FPGA and Im hoping I can get some insight on this problem.
I'm using the PLB_DDR2 xilinx ip core to interface two DDR2 memory. Currently I can read/write to DDR2 memory through the XMD/JTAG debug port. I then do a soft reset of the system by an "rst" command through the xmd command prompt. All my internal registers reset correctly and I can read/write to them. Hovvever, if i then try to read/write to DDR2, the system crashes and i get weird values back. A soft reset will bring back register access, but I have to reprogram the FPGA in order to get DDR2 read/write capability.
It seems like for some reason the DDR2 controller is not being reset with the rest of the system.
Thanks for any suggestions on this.