Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
device selection for game system
I'm working on implementing a custom game boy advance cartrige with the following features: - 4-16MByte flash rom (bank switched to a 24 pin buss) - 32kbyte save ram (game state save, can be stored in...
 
EDK/XPS/Virtex2Pro - TFT core not avaialble
Hi I am trying to use xilinx PLB TFT LCD core with EDK/XPS but the core is not even listed, it is in the cores directory (marked obsolete) ML300 TFT works well with xilinx demos, but there is no EDK...
1
1
 
NAND flash file
Does anyone know where I can find the xapp354_verilog or xapp354_VHDL files for NAND flash? I went to the Xilinx ftp site, and they were not listed there. Thanks.--Matt
1
1
 
Re: why so many problems Xilinx ?
I cannot understand that at all. If the question is ventilated in public, it should be answered in public. Unless the answer is very embarrassing... Peter Alfke, Xilinx
8
8
 
Re: NgdBuild:477 - clock net xx has non-clock connections
Thomas, Ngdbuild is warning that what it thinks is a clock (but is actually a reset) is not connected to clock pins of various components. When I have seen this warning it was usually as a result of...
 
Re: Xlilin xc9572XL Default register values
Ralph, Sorry for the delay in my response. I tried the code below with ISE 5.2i sp3 targeting a 9572: library IEEE; use entity inits is Port ( d : in std_logic; c : in std_logic; q : out std_logic);...
1
1
 
Seriell Decoder possibly in ABEL for Lattice CPLD
Hi there I'm not very familar with HDL, but I have to realize a small project with Lattice CPLD. Up to now the most things are working fine, but now I need help: I'm searching for a device to...
1
1
 
Re: SPARTAN-3 vs. VIRTEX-II
You can feel how you wish about your designs, but even the loss of the 64 bit dual ports and the 128 bit single port rams is not signficant. To make a 64 bit dual port RAM requires 8 LUTs for ram...
9
9
 
Re: Dynamic Reconfiguration, Virtex II Pro
Hi tk, thanks for your reply. I had to get more familiar with the the buff-stuff. An ibufg is just a dedicated input buffer for connecting to the clock buffer BUFG or clock problem was solved with the...
 
Xilinx ISE drops support for more parts
I am reposting after a memo from reader siting problems using the Xilinx link to post to this group. Sorry about any problems this may have caused. After the release of Alliance 3 support was no...
30
30
 
Re: MIPS instruction set?
As far as I know, its the same core of the Toshiba TX7901 micro processor, and it has 32 (of course, it´s a MIPS) 128 bit registers, although the two integer units are 64 bits wide. Only the SIMD...
 
Re: the skew and race condition
There is skew even in dedicated clock lines. Because clock nets are dedicated for just for clock signals skew is much smaller and can (more easily) be accounted for in place and route. Most FPGA tools...
1
1
 
Celoxica DK1 to Xilinx Spartan II
Hello, I have written a program to run on the Celoxica RC100 board and compiled it to edif file. When i use the Xilinx Design Manager to convert it to a bit file, it always fail during the mapping...
1
1
 
I need a commercial PCI FPGA board, please help
I need an FPGA board with a 64-bit 66MHz PCI bus and Linux drivers, and I need to be able to demo it, and I need it fast. If that's not demanding enough I can add more requirements. I have looked...
5
5
 
Eighty layers of metal!
Article intended for FPGA-types has a nice summary (for dummies like me) of the state of the wire-delay/interconnect problem: "James Meindl at the Georgia Institute of Technology, who has become an...
5
5