Best Rated threads in Field-Programmable Gate Arraysshow all threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
Microchip UNI/O controller core for FPGA
Hi, I needed to access the Microchip 11AA02E48 EEPROM located on a FPGA board. Unfortunately, I couldn't find any VHDL/Verilog sources of a UNI/O controll er. Therefore, I have decided to write my...
—
|
4 years ago
|
— | |
|
|
VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free - and open source
UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectures....
—
|
7 years ago
|
— | |
|
|
Lowest Power Design in an FPGA
What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that push...
2
|
11 years ago
|
2 | |
|
|
Call for beta users for Sigasi integration with Altera Quartus
Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We have...
—
|
11 years ago
|
— | |
|
|
ICTP Open Hardware Initiative – Invitation to part icipate in an open-survey.
Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP -...
—
|
12 years ago
|
— | |
|
|
Software for FPGA-based PC scope
Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in...
18
|
16 years ago
|
18 | |
|
|
lowest-cost FPGA and CPLD
I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give me...
4
|
19 years ago
|
4 | |
|
|
Job - Promotion - 2D/3D Bildverarbeitug - FPGA
Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folgenden...
—
|
9 years ago
|
— | |
|
|
Avnet Virtex-4 FX12 mini module
Hello, I have recently bought Avnet Virtex-4 FX12 mini module. I am trying to implement the Gigabit ethernet communication between the FPGA and the host PC. Can anyone give me some hints to get...
5
|
17 years ago
|
5 | |
|
|
JTAG programming of Altera Cyclone and CONF_DONE
All, I'm having an extraoridnarily difficult time with my first FPGA project and am very frustrated. I have a board designed around the EP1C6 Cyclone device. The Quartus programmer is able to detect...
10
|
17 years ago
|
10 | |
|
|
Cyclone I & II memory fmax
Hi group, using a 128x32 bit simple dual port memory with independent read and write clock results in following fmax for both clocks (dout is registered): Cyclone (I) 256 MHz, Cyclone II 210 MHz...
6
|
17 years ago
|
6 | |
|
|
current price for (small quantity) XC4VFX12/FF668
Just trying to figure out what the rough price of V4 FX12/FF668 part is... AVNet and NuHorizons aren't showing any prices or stock atm, and digikey don't do anything even vaguely recent :-( Anyone...
5
|
18 years ago
|
5 | |
|
|
how to set the ISP mode for programming CPLD?
Hello, I need to program CoolRunner CPLD using an embedded controller. How to set the CPLD registers to work in the ISP mode? Please explain how to do. Regards, Chi
2
|
20 years ago
|
2 |