Xilinx Virtex IOB Regiters and Noise???

I am registering a data bus at the input of a Xilinx Virtex FPGA (XCV300) using IOB registers. It appears that some of the register bits are locking in incorrect data.

All registered bits are brought back out of the device for debug purposes. When looking at logic analyzer waveforms, it appears that the data bus coming in is stable, yet a few bits inside the FPGA are registered incorrectly. We have tried to adjust the signal level of the logic analyzer to look for glitches on the input data bus but do not find any.

All we can figure is that there must be some ringing or transmission line effects on the data bus. Are the Xilinx IOB registers particularly sensitive to noise? What other effects could lead to registering the incorrect value? It appears that the setup time for the data bus is approximately 7.5 ns, so that is much greater than the Xilinx spec of 2.1 ns setup.

ANy thoughts would be appreciated.

Reply to
Analog_Guy
Loading thread data ...

Check the timing of your clock relative to your data on the FPGA and check your Timing Analyzer "Data Sheet" section for the setup and hold times. Are they compatible?

I'd bet that your problem isn't noise but a matter of missing the clock cycle and getting the bit before or after the cycle you expect (or not at all depending on how you're sampling your data).

- John_H

Reply to
John_H

If you suspect ringing or glitches I'd look with a scope instead of the logic analyzer. When you say the bus is stable, do you mean a bit that hasn't changed state is registered at the opposite state?

What about hold time? Are the input registers using the built-in delay path? What does the post P&R timing report show for hold time requirement on these inputs?

All Virtex registers are fast in terms of capturing glitches. Another thing to look at with a scope is the rise / fall time of the input signal. Logic analyzers tend to mask this. Maybe you don't have as much setup time as you think if the Virtex and logic analyzer don't use the same threshold levels.

HTH, Gabor

Reply to
Gabor

I will have to get a scope, but for the time being ... the data bus coming in does not change state, yet some bits are registered at the opposite state for 1 clock cycle (@ 60 MHz).

The data sheet report shows that the setup times for all data bus bits are 1.958 ns, and the hold times are -1.006 ns.

I will have to instrument a scope to look at the rise times ... thank you.

Reply to
Analog_Guy

So this seems critical ... during a period where data is supposed to be quiesent, you are detecting spurious false states. So this sounds not like a timing problem, but some "noise problem"/power supply/misc gremlin problem.

To answer your original question, I have been using Xilinx devices for 10 years, and before they are released for general use, they are pretty bullet proof. However, there are lots of pwb/power supply device interconnect issues that can cause related problems.

Here are some things to do :

[1] Take a look at the input signal with a scope .... make sure HI/LO voltage levels match what FPGA expects. [Look at the .pad file in synthesis directory. This defines the electrical interface for the input signal. Adjust the trigger, and see if there are spurious events on signal input. [2] Verify the Bank Voltage on the device is correct. [3] Are single clock events permissible? If not, use something like the following snippet as a "debug trigger".

wire debug_trigger = signal[2] & ~signal[1] & signal[0] | ~signal[2] & signal[1] & ~signal[0]; always @ (posedge clk) begin signal_q Thank you for your responses.

Reply to
John Retta

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.