Hi, Now, I learn xflow of xilinx. I want to generate a function simulation output file. For the example vhdl file: watchvhd, according to the Development System Reference Guid, I use the command:
xflow -p xc2vp2-7fg256 -fsim modelsim_vhdl.opt stopwatch
It generates a file: func_sim.vhdl
My question is: How can I use it in Modelsim? Thanks in advance
Hi Fl,
The term functional simulation is kind of misleading. What you will get is a post translate netlist when you run this. This will synthesize your design run through ngdbuild and then run netgen to give you a structural netlist of your design. If you want to run a pure functional simulation then you probably want to use RTL files.
Once you have the netgen output file, just compile it in modelsim and run the simulation with your testbench.
Xilinx Reference Solution Record: 1078
Hope this helps Thanks Duth
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