PCB Layers

Hi

I am designing a pcb with a Virtex 4 FX in a FF672 package. Is there general rule of how many layers the pcb will need to route out all th pins?

Cheers

Jon

Reply to
maxascent
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In the Virtex 2 users guide there are suggested breakout routings for each package. There should be similar documentation for V4. Note that your layer count will depend on the design rules you choose for pcb manufacture. At 1mm spacing, you may need to reduce your via drill size to 10 mils (gotta love mixed units of measure) and leave out unused pads on inner layers to allow more routes between adjacent pads. With 5 mil width and spacing and 12/25 mil via drill/pad you can only run 1 line between pads.

We've made boards using similar dense packages using from

8 to 12 layers depending on design rules. For at least the suppliers we use, saving layer count reduces price significantly even if you need to use fine (10 mil) drills.

Suggested breakout patterns also require dogbone removal on the outer two rings of pads. Be sure to run unconnected outer pads to a test point since you won't be able to access them without the dogbone / via.

After you look at the breakout drawings, don't forget to add the appropriate number of plane layers to deliver all of your supply voltages. You may need more than 1 ground plane depending on your I/O switching rates.

Good Luck, Gabor

Reply to
Gabor

Jon, In my experiance I have found that the answer to your question is....it depends :)

The total number of PCB layers is dependent on all components, voltages, and signaling types utilized on the board. If you have strict requirements on isolation and noise then the count goes up. Looking at it from a signal layer count for supporting of the FPGA only, I have found that n/2 is a good approximation, where n is the number of rows to get to that center point of the package. I guess you could say the total number of rows for the package divided by 4. That is most likely your minimum number of signal planes. Again, the whole thing is academic, because each design is different. If you have not utilized 100% of the I/O, then your count might be lower. If you have used 50% of the I/O, but it is all in a few banks, then you will need to use more layers than if the I/O had been spread over the entire package. Finally, look at the requirements for your other components. Analog devices usually have different voltages, or multiple ground requirements that can greatly influence your stackup.

Good luck, vt2001cpe

Reply to
vt2001cpe

We've done Spartan3 FG456 chips on 6 layers, so you'll probably need 8 or 10. Start sketching!

John

Reply to
John Larkin

Thanks for all the info. I think I may be able to get away with using 8 a not all of the banks are fully utilised.

Jon

Reply to
maxascent

Use laser drilled microvias. You'll save the extra money they cost on by reducing the number of layers by 4. You only need them on the same side as the BGA. Layer 1 Layer 2. All the other vias can be through. HTH., Syms.

Reply to
Symon

If do you have to route GTPIO transcievers and you'll probably want stripline then 8 layers could be at limit.

Vasile

Reply to
vsurducan

Hi Gabor, Could you point to a picture showing this tehnique ? I don't understand what exactly means "dogbone removal".

thx, Vasile

Be sure to run unconnected

Reply to
vsurducan

This sounds interesting. Are you using via-in-pad? Can you point me to a good source showing how to use microvia's to improve BGA routing? A quick Google search brought up lots of articles that assume you already know the basic premise. Just at first glance I would think that the inner portions of the BGA routing would still require traditional techniques?

Regards, Gabor

Reply to
Gabor

At 1mm pitch, microvias in pad will not be a very good option. I've used microvia in pad for 0.65mm pitch and it was very expensive. There must be a low isolation thickness between layer 1-2 for microvias, and usually the board is requesting simmetry (if you have microvias on 1-2 then you may have on 7-8 but depends on stack).

Vasile

Reply to
vasile

Most other posts are focussing on signal routing. But for FX this really is the least of your problems. The answer depends a lot on the MGT performance you are looking at. The MGTs need many supply voltages. Each of them should be filtered individually for high data rates. This means you either need many islands, which reduce plane capacitance and increase plane inductance. Or you need many, many planes. For lower data rates (1.25gbps) you should be able to combine supplies that have the same voltage. This is not recommended by Xilinx, so your milage might vary.

Also, the MGTs pretty much prevent routing out signals on the top layers. As a result, an FX that uses all MGTs will need more layers than an LX. We use 14 layers for an FX60-FF1152 with 12 MGTs at 5gbps.

Kolja Sulimma

Reply to
comp.arch.fpga

And put something in the silk on the back because you will always forget this when you start counting off the vias to find a particular pin...

--
Ben Jackson AD7GD

http://www.ben.com/
Reply to
Ben Jackson

Have you do it only with through and blind holes without any backdrilling ? The MGT are using striplines for long routes and microstrip for escaping ? Have been used AC coupled or DC coupled MGTs ?

thx, Vasile

Reply to
vsurducan

Hi Gabor, Yes, I use via in pad. There's an article here all about it:-

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Void formation is seen as bad. My experience is otherwise. I've made boards with microvias dead centre of the pad, offset from the pad, and Cu filled microvias in pads. If there was a yield difference between these methods, my production team and service guys kept quiet about it. (They sure moaned like crazy when the QFNs had problems with pad size!)

I posted about this three years back, Google for "PCBs for modern FPGAs" in CAF.

Here's a link to a picture of board I did then :-

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(Thanks to Philip for keeping it there!)

If you have 0.1 mm tracks 'n' gaps and make the BGA pad size 0.5mm, you can get the first 3 layers out on layer one. Then work back from there, layer 2 can take perhaps 4 traces/mm. That lets you go 7 balls deep from the edge without a through via. The powers and grounds use through vias. I try to keep the through vias on the 'corner' of the destination pad nearest the centre of the BGA, this facilitates the routing of the signal traces outwards. The backside of the board can be covered with bypass circuitry as there isn't the usual field of through vias filling this area.

(BTW., I did once use slightly bigger pads, but made the outer balls oval to get the traces out. Again this made no detectable yield difference.)

The gap between layers one and two is necessarily small for microvias. This is great news for SI; the laser drilled via has only a tiny inductance, and the reference plane for layer 2 is the same as layer 1. Except in a microvia board it isn't drilled with so many holes!

I've done many boards with microvias on one side only. (Keep the BGAs on that side!) This way you can keep the price down. The stack up needs to be symmetrical, but the distribution of planes doesn't. See the post from three years ago for details.

Also, you can get a lot more stuff on a given sized board. Through vias get in the way of mounting stuff on the backside of a board, the microvia alleviates this problem.

And be prepared to swap pins on the FPGA when you do your layout. This saves time in layout, and I know that PADS has a magic feature to assist in this.

In all, I find I get cheaper (fewer layers) and more compact boards, with better SI, by using this technology.

HTH., Syms.

Reply to
Symon

Hi Vasile, I'm sorry you didn't have a good experince with the technology. Mine has been somewhat more positive. I spend more on the laser vias, but claw that back and more with the layer reduction. Also, I only need a symetrical stack to keep warpage low. The microvias do not need to be on both side of the PCB. I don't do that unless I have to. Finally, I find the "low isolation thickness between layer 1-2" is a very good thing for SI. GHz traces don't 'notice' microvias, and stay referred to the same plane. HTH., Syms.

Reply to
Symon

Hi Kolja,

Although your suggestions will result in a working solution, I respectfully think you're overengineering this. The power supplies to the MGTs don't need islands or a plane. A 0402 cap right by the ball, fed from a ferrite is as good bypassing as you're going to get. The ferrite can be on the reverse side or far away from the device. All the stuff you read about plane capacitance is over-rated for bypassing ICs, including BGAs. The inductance of the BGA's balls and connections to the die stuff means that the admittedly ultra high Q of the plane capacitance is not much use at all, so why bother even trying? In this situation, with the power pins neear the edge of the part, it's much more useful to keep the ground plane as close to the surface as possible, than to worry about power planes.

The microvia solution works perfectly for MGTs as these vias are more or less transparent to very high speeds indeed.

Anyway, that's my experience.

HTH., Symon.

Reply to
Symon

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Symon, do you follow the recommended filtering from the Xilinx MGT guid i.e. caps and ferrites next to the BGA for all the supplies?

Jon

Reply to
maxascent

It can also be non-existent (i.e. tie right to the power plane instead of putting the series ferrite in). The ferrites are a band aid to not having a low impedance voltage source feeding the IC in the first place. Design the planes to have the proper impedance to deliver the required current over the operating frequency range in the first place and the voltage ripple will be within spec and you'll rightly start to question just what the ferrites bring to the table.

But if you insist on ferrites, don't forget that they are basically inductive (by intent) and then be careful about your bypassing caps since those Ls and Cs do form a resonant structure that is more likely to cause a problem with a poor choice of C then the plane was in the first place. In other words, the 'output side' of the ferrites need to have the same set of low/mid/high frequency range bypass caps as you (hopefully) already provided on that supposedly nasty, noisy 'input side'.

It provides a low inductance current source but is not a relatively deep bucket of charge to draw from due to the low C/area. In any case, whether a full plane or strip it has some L and C and therefore Z that contributes to the IC's view of the voltage source...along with the bypass C and the PCB stackup, etc.

I'd say, bother to analyze it first to determine what the Z requirements of the PCB need to be to source the power than to just blindly say why bother trying....but from earlier posts I also know you've done this as well so probably have a better grasp of the issues and tradeoffs in the first place.

KJ

Reply to
KJ

Hi Jon, Yes for the caps and ferrite. I disagree with their recommendation for linear regulators to filter the supplies as these regulators do not have sufficient bandwidth to control noise > a few 100kHz. I use passive filtering also to cover the range from the linear regs up until the ferrites work. HTH., Syms.

Reply to
Symon

Hi, some comments in line...

Remember that the ferrites are useful in both directions. Not only to they stop noise getting to the MGT, but prevent the noise from the MGT getting back to the supply and interfering with other stuff powered from it.

OK, but ferrites are deliberately lossy. A useful model is an indcutor in series with a resistor. This means bad resonances don't happen with ferrites.

Cheers, Syms.

Reply to
Symon

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