Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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How to define multi-cycle timing constraints in Lattice iCEcube2 (synplify)
In a design, I have a number of counters that have an enable that is only active every N periods of the clock signal. With only a clock of 200MHz in the timing constraints, the counters are assumed to...
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9 months ago
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Foundation 1.3/XactStep 6 dongles and licensing
I need to generate a programming file for an older XC7300 series chip using an existing Abel and/or PLD file. As far I know, only XactStep 6 and Foundation 1.3 supported those chips as Foundation 1.4...
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10 months ago
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Embedding a Checksum in an Image File
I am not sure what your intended use-case is here. But it is very common to add a checksum of some sort to binary image files after generating them. This is done post-link. You have a struct in your...
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1 year ago
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What happened to the OpenCores website
Am 18.01.23 um 16:32 schrieb same here. But the deep link to my sine/cos-table and the DDS still works. < > Gerhard Overview :: SineAndCosineTable :: OpenCores Overview :: SineAndCosineTable ::...
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1 year ago
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Re: PCB Layout for BGAs
It's difficult to know the impact without knowing details of the board you have at the moment. It is also somewhat dependent on the layout of the balls on the part - some BGA's have missing balls, or...
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1 year ago
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Trion bitstream compression test
Suppose we read in an FPGA bitstream file as 16-bit words, and want to output a compressed file, to save room in a small flash chip. If an input word is 0000, output a single 0 bit to the compressed...
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1 year ago
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Re: Program Counter in Verilog. Case not working.
All possible case values need to be in the code. pc_mode[2:0] allows for 8 values and your code only has 5. You can add a one default case for the ones you don't need instead of adding each...
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1 year ago
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Disabled generate gives compile error in Modelsim
[This is a repost. Posted this to a few days ago, but no replies. So maybe nobody knows the answer, it was a malformed question or there are no readers in that group. So a repost (with a little...
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1 year ago
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Developing older Xilinx FPGA and CPLD XC3S500E
The latest version of Xilinx ISE, 14.7, runs on Windows 10 and supports Spartan 3E. I always used ISE from the Project Navigator GUI, but I believe you should be able to run your command line builds...
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1 year ago
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efinix bit stream question
We use the efinix T20 trion FPGA. Questions about the config bit streams: Are they always the same size, or does it depend on how much logic is compiled? Would a simple application use less? Are the...
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1 year ago
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Re: Renesas has a 1 kLUT FPGA!
What does it add to the usual CPLD offerings? I see there's some BRAM, which could come in handy, although 1kLUT isn't a great amount to make use of it. And it comes in QFN24, which is nice. Although...
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1 year ago
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Re: Intel announces new FPGA families
I think the FPGA market has bifurcated into (at least) two quite distinct markets: - the small, low cost, low power segment, where people want a programmable chip of the scale of a small CPU like a...
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1 year ago
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Re: Hardware based IP protection of FPGA designs
Microsemi, now Microchip, has FPGAs that the programming tools can be setup to need authorization keys to program a specific number of devices. The system is designed for this sort of environment,...
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1 year ago
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Wide frequency range, arbitrary waveform DDS
To generate frequencies from approximately 0.5 mHz to 12 MHz with a DDS a minimum clock of >24, say 25 MHz, is required. To be able to go down to 0.5 mHz, a phase accumulator of at least 36 bits is...
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1 year ago
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Efinix FPGA
Anyone using Efinix parts? They look ok, even if they don't have a lot of package offerings. The smallest part has a 0.5A surge at power on. The list it as "minimum", I'm guessing they mean the...
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1 year ago
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