Field-Programmable Gate Arrays

Interesting FPGA/JTAG project.

Guys, I saw this on Slashdot. http://nsa.unaligned.org/ Interesting article about a guy who used some rescued FPGA board...

0 comments posted 18yrs

posted by symon_brewer

0 comments posted 18yrs posted by symon_brewer

How to add additional FSL interface to customized IP?

Hi, I would like to create a system like below: uBlaze customized IP uBlaze Could anyone tell me whether it is possible...

1 comments posted 18yrs

posted by jogchen

1 comments posted 18yrs posted by jogchen

Chip Designing made Easy

Chip Designing Made easy To Understand the "World of Miniaturization" and Appreciate the "Art of Chip Design" a senior...

2 comments posted 18yrs

posted by robinhood143

2 comments posted 18yrs posted by robinhood143

BlockRAM connection error

Hi all, I met a wired BlockRam connection error when I tried to build a mutilple processors system using EDK. Hope anyo...

0 comments posted 18yrs

posted by zhang.young

0 comments posted 18yrs posted by zhang.young

what does asynchronous loop mean?

Is it bad to have async loop? If so, why?

1 comments posted 18yrs

posted by asic1234

1 comments posted 18yrs posted by asic1234

Xilinx ML40x Mouse VHDL Wanted

Does anybody have VHDL code to run the mouse port on an ML40x dev board? Brad Smallridge Ai Vision

1 comments posted 18yrs

posted by bradsmallridge

1 comments posted 18yrs posted by bradsmallridge

signal termination in spartan 3e starter kit

hi i am new to FPGA designs. i have a question about signal termination. the spartan 3e starter kit has a 10 ohm resist...

0 comments posted 18yrs

posted by asimatta

0 comments posted 18yrs posted by asimatta

Simple Project involving microblaze

Hello Everyone! Can anyone suggest a simple exemplary FPGA project involving microblaze using ISE tools rather than EDK...

1 comments posted 18yrs

posted by amiri.amir

1 comments posted 18yrs posted by amiri.amir

Memory bandwidth of the 3A kit

Antti, did you ever get a feel for what memory bandwidth you actually get with this setup ? For example, if you had a b...

2 comments posted 18yrs

posted by google

2 comments posted 18yrs posted by google

Wifi with a Virtex 4

Dear all, I'm just starting to look into the possibility of adding 802.11g to one of our products which is based on a V...

0 comments posted 18yrs

posted by petermendham

0 comments posted 18yrs posted by petermendham

Is it possible to make bit files generated by Xilinx ISE readable?

I thought the bit files generated by Xilinx ISE should be in plain binary format, but actually the .bit file is unreada...

4 comments posted 18yrs

posted by camwwang

4 comments posted 18yrs posted by camwwang

Xilinx blockram FIFO async reset annoys me (and Modelsim)

Hi all, I'm facing a problem with Xilinx Coregen blockram fifo. At some point I want to reset it with a signal generate...

0 comments posted 18yrs

posted by maybetooparanoid

0 comments posted 18yrs posted by maybetooparanoid

Spartan 3E - Readback via JTAG

Hi, i'd like to readback all the contents of an XC3S500E via the JTAG interface. Because this option is not implemented...

3 comments posted 18yrs

posted by benniv.sep08

3 comments posted 18yrs posted by benniv.sep08

An FPGA startup is seeking testcase from potential customers

Hello, Silicon Blue Technologies is an FPGA startup located in Sunnyvale CA. The FPGA product it is developing has ultr...

4 comments posted 18yrs

posted by siliconbluetechnology

4 comments posted 18yrs posted by siliconbluetechnology

Die size, pitch size?

Dear When I look at Virtex-II Pro data sheet (DS083 v. 4.5), page 7, I see following table. ------------------------- P...

13 comments posted 18yrs

posted by pasacco

13 comments posted 18yrs posted by pasacco