VHDL core to read/write to Bram_Block.

Aug 29, 2007 3 Replies
P

Hi, I have implemented a core to write/read to a Bram_Block (using one of the two ports). The another port is used by Microblaze with a lmb_bram_if_cntlr core to read those values which had been modified by my custom core. Of course, I use a lmb bus.



Now, I want to create a design with PowerPC and I suppose I must use a plb bus to access to the bram_block. With this assumption, PowerPC would use a plb_bram_if_cntlr core to read from the bram (this works fine), but my custom core cannot modify the contents of the bram.



What's wrong?. Is plb bus very different from lmb?. Could I use a lmb bus with PowerPC instead of Microblaze?



Best Regards



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G

Hi,

You should be able to use the plb_bram_if_cntlr. You might need to look at the size of the data busses, The BRAM implemented will not handle different sizes on the two ports.

Göran

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H

Hi Pablo,

I want to ask u how u are able to read the block ram by microblaze.

U said u had used lmb_bram_if_cntlr core to read the BRAM. then r u using the same lmb bus used by microblaze to access data( in instruction). Then in C code which instruction u had used to read BRAM data.

Would u please explain ur design

Thanks and regards, Harshada

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P

Of course. You have to create a bram block and the a core to access it with PortA (for example). I have use lmb bus and lmb core. Finally you have to export to ISE and add another "custom" core in vhdl to access to the another port (in this case B). It's very simple.

Best Regards. Pablo

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