Field-Programmable Gate Arrays

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Embedding a Checksum in an Image File

This is a bit of the chicken and egg thing. If you want a embed the code checksum in a code module to report the checks...
1 comments posted 3yrs
posted by gnuarm.del...
1 comments posted 3yrs posted by gnuarm.del...

What happened to the OpenCores website

I have noticed, that the categories on the list of projects https://opencores.org/projects do not unfold after clicking...
1 comments posted 3yrs
posted by wzab01
1 comments posted 3yrs posted by wzab01

Re: PCB Layout for BGAs

> A small board with a 100QFP is being redesigned for a new FPGA due to > obsolescence. Gowin makes a 100QFP device tha...
27 comments posted 3yrs
posted by david.brown
27 comments posted 3yrs posted by david.brown

Trion bitstream compression test

Suppose we read in an FPGA bitstream file as 16-bit words, and want to output a compressed file, to save room in a smal...
4 comments posted 3yrs
posted by jlarkin
4 comments posted 3yrs posted by jlarkin

Re: Program Counter in Verilog. Case not working.

> Hello All, > > I'm just getting started with Verilog. > I created the following Programs Counter for a simple Stack M...
1 comments posted 3yrs
posted by charlieDOTd
1 comments posted 3yrs posted by charlieDOTd

Developing older Xilinx FPGA and CPLD XC3S500E

I have some old chips and in light of the shortages I continually see despite the 52 week lead time thrown around in th...
1 comments posted 3yrs
posted by taylor.cybel
1 comments posted 3yrs posted by taylor.cybel

efinix bit stream question

We use the efinix T20 trion FPGA. Questions about the config bit streams: Are they always the same size, or does it dep...
10 comments posted 3yrs
posted by jlarkin
10 comments posted 3yrs posted by jlarkin

Re: Renesas has a 1 kLUT FPGA!

> I guess I've heard something about this before, but it must have bounced off and not sunk in. Here's the data sheet....
0 comments posted 3yrs
posted by theom+news
0 comments posted 3yrs posted by theom+news

Re: Intel announces new FPGA families

> > > https://fpgaer.tech/?p=561> > Maybe I'm just old, but it seems to me "new" in the FPGA world is not very > inspir...
0 comments posted 3yrs
posted by theom+news
0 comments posted 3yrs posted by theom+news

Re: Hardware based IP protection of FPGA designs

> My customer is asking for a redesign of a very profitable board to deal with components that are EOL. Because of deli...
5 comments posted 3yrs
posted by Richard
5 comments posted 3yrs posted by Richard

Wide frequency range, arbitrary waveform DDS

To generate frequencies from approximately 0.5 mHz to 12 MHz with a DDS a minimum clock of >24, say 25 MHz, is required...
22 comments posted 3yrs
posted by me
22 comments posted 3yrs posted by me

Efinix FPGA

Anyone using Efinix parts? They look ok, even if they don't have a lot of package offerings. The smallest part has a 0....
16 comments posted 4yrs
posted by gnuarm.deletethisbit
16 comments posted 4yrs posted by gnuarm.deletethisbit

Getting Rank of Elements in an Array using VHDL

Dear VHDL Coders, I am trying to get the rank of elements from an array of data. For example, I have an array, Voltage...
1 comments posted 4yrs
posted by multan.ieee
1 comments posted 4yrs posted by multan.ieee

Development tools for Xilinx Spartan 3

For support of an old product, we may need to modify a Xilinx Spartan 3 FPGA. This was originally designed in VHDL with...
4 comments posted 4yrs
posted by me
4 comments posted 4yrs posted by me