Field-Programmable Gate Arrays

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memory in spartan 3 fpga

Hi, I'd like to set up block rams(16k) to acts as a ROM lookup table after initialization. After establishing the Memor...
2 comments posted 19yrs
posted by vkmselva
2 comments posted 19yrs posted by vkmselva

intialize memory in fpga

I'd like to set up block rams(16k) to acts as a ROM lookup table after initialization. After establishing the Memory Ar...
3 comments posted 19yrs
posted by vkmselva
3 comments posted 19yrs posted by vkmselva

Question about xflow?

Hi, Now, I learn xflow of xilinx. I want to generate a function simulation output file. For the example vhdl file: watc...
1 comments posted 19yrs
posted by rxjwg98
1 comments posted 19yrs posted by rxjwg98

Strange behaviour of a design

I am working now for some days on a strange behaviour of a fpga. The design is complete synchron. I have the problem th...
9 comments posted 19yrs
posted by markus.jank
9 comments posted 19yrs posted by markus.jank

VHDL core to read/write to Bram_Block.

Hi, I have implemented a core to write/read to a Bram_Block (using one of the two ports). The another port is used by M...
3 comments posted 19yrs
posted by pbantunez
3 comments posted 19yrs posted by pbantunez

Problems with PLB_DDR2 core and soft reset

I'm developing an embedded PPC405 system on a Xilinx FPGA and Im hoping I can get some insight on this problem. I'm usi...
4 comments posted 19yrs
posted by JimboD2
4 comments posted 19yrs posted by JimboD2

VGA controller in the EDK ?

Could some kind soul please tell me if there's a Xilinx-supplied VGA controller in the EDK ? Looking on http://www.xili...
4 comments posted 19yrs
posted by google
4 comments posted 19yrs posted by google

PCB Layers

Hi I am designing a pcb with a Virtex 4 FX in a FF672 package. Is there general rule of how many layers the pcb will nee...
19 comments posted 19yrs
posted by maxascent
19 comments posted 19yrs posted by maxascent

Xilinx Virtex IOB Regiters and Noise???

I am registering a data bus at the input of a Xilinx Virtex FPGA (XCV300) using IOB registers. It appears that some of...
4 comments posted 19yrs
posted by analog_guy
4 comments posted 19yrs posted by analog_guy

VHDL clocking scheme VS Verilog clocking scheme

Hi, I am confused about the clocking scheme of the two most popular hdl. The most common usage of clock and reset signa...
3 comments posted 19yrs
posted by anilcelebi
3 comments posted 19yrs posted by anilcelebi

XHWIF interface for Virtex II devices

Hi, I was wondering if anyone has implemented the XHWIF interface for any Virtex II device in other words the C/C++ dll...
0 comments posted 19yrs
posted by shadabambat1
0 comments posted 19yrs posted by shadabambat1

weird issue on Xilinx ML501/ML505 evkit designs

Hi, Usually I do not post such questions but I've got no answer from Xilinx and I want to be sure I have right. I've to...
0 comments posted 19yrs
posted by piclist9
0 comments posted 19yrs posted by piclist9

New keyword 'orif' and its implications

Hi, I open a new topics from previous one to try to stir another round to introduce a new keyword 'orif'. > > Hi Mike,...
64 comments posted 19yrs
posted by wtxwtx
64 comments posted 19yrs posted by wtxwtx

PLL Power and m/n ratio

Hi Folks, I am wondering the implications on PLL power compared to the m/n ratio that is used to generate a particular...
6 comments posted 19yrs
posted by fpgabuilder-groups
6 comments posted 19yrs posted by fpgabuilder-groups