Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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How the synthesizer acutally works.
Hi guys, To know how the synthesizer behave,i wrote logic to add 4 vectors in three different i got differnet result from the synthesizer(used both ISE and synplify). These are the three different...
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16 years ago
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M-RAM allocation in Stratix EPS125B672C6
Hi , I am using Altera Quartus II version 4.0 . The EPS125 device has 138 M4K blocks 224 M512 blocks 2 number of 512K Mram blocks has a total of 1,944,576 bits. ( ) the problem i am facing is i am...
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16 years ago
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Design running on board but timing are not met
Hi All, I have developed a design which obtained max freq. 56Mhz. So i applied global clock constraint to implement design and timimg is met. This design has sub-modules which are running above...
2
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16 years ago
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LVCMOSS33 I/O sink current
I am using spartan3 fpga with lvcmos33 output pin set to 16 mA drive strength and fast slew rate. I am assuming that 16 mA is the source current at 3.3V as my VCCO voltage is 3.3V. I would like to...
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16 years ago
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JTAG FPGA Debugging
Hi everyone! I'm new to the group and quite a beginner in FPGA business. I have this very general question on BSDL files and JTAG - is there any possibility to include any internal signal (not...
5
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16 years ago
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how 33-bit BRAM?
Hi I need to implement 33-bit data BRAM. Obviously, following BRAM will not work. Does anyone suggest how to implement 33-bit data, if possible? Thank you in advance. component RAMB16_S36_S36 port...
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16 years ago
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ISE Service pack
For some reason i am not able to download ISE service pack for 9.1i version. Can any body upload it ?
1
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16 years ago
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System-synchronous interface clocking between FPGA's
This may seem like an elementary question/application, but I'll bring it up nonetheless in hopes of getting a thorough understanding... In our design, there are 80MHz system-synchronous interfaces...
5
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16 years ago
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"black_box"-ing of components in toplevel
Hi again, What does the setting of the attribute box_type to "black_box" for my toplevel components effect (concerning modular design flow)? Syntax checking in ISE projnav searchs for the components'...
3
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16 years ago
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Problems to simulate (behavioural) in XPS
Hi friends, I am working with Solaris and with all the systems that i generate with XPS have the same problem. I have a Problem with LIBGEN. If I execute XPS->Software->generate libreries and BSPs,...
12
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16 years ago
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Problem with DDR2 controller
Hi to all I am currently working on DDR2 controller for Burst Lenth 8. My own code is giving good results when i verified with memory model from MICRON. Now my problem is memory on the board is not...
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16 years ago
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PLB behaviours strangely during burst transactions
Hi, I'm using PLB to read and write 64bit data through burst transactions. I can read and write data correctly, but watching the signals through chipscope I can see a strange behavior: the PLB_MWrDAck...
5
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16 years ago
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PLB behaviors strangely during burst transactions
Hi, I'm using PLB to read and write 64bit data through burst transactions. I can read and write data correctly, but watching the signals through chipscope I can see a strange behavior: the PLB_MWrDAck...
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16 years ago
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using FPGA JTAG as GPIO
Hi I want to debug a custom board with no interface for data exchange. The requirement is PC based autometic test pattern generation and real time data exchange from FPGA based hardware. I chanced to...
1
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16 years ago
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DDR Controller Blue
Dear all, I am working on a DDR controller that stores captured video frames from which a VGA controller retrieves data. It (DDR controller) works fine for the first few frames but seems dead...
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16 years ago
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