Problems to simulate (behavioural) in XPS

Hi friends,

I am working with Solaris and with all the systems that i generate with XPS have the same problem.

I have a Problem with LIBGEN. If I execute XPS->Software->generate libreries and BSPs, gmake ist not compiling the libraries and the directory ./ppc405/include possesses only the file xparameters.h and the directory ./ppc405/lib is empty

*************************************************************************** XPS INFO: Configuring make for target include using: gmake -s include "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi- ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g"

gmake: Command not found. gmake: Command not found. gmake: Command not found. gmake: Command not found.` gmake: Command not found. gmake: Command not found. Configuring make for target libs using: gmake -s libs "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" gmake: Command not found. gmake: Command not found. gmake: Command not found. gmake: Command not found. gmake: Command not found. gmake: Command not found. Libraries generated in /home/ferorcue/my_work/project/xps/xps_lin_v1_e/ppc405_0/lib/ directory Running execs_generate for OS'es, Drivers and Libraries ... LibGen Done. powerpc-eabi-gcc -O2 TestApp_Memory/src/TestApp_Memory.c -o TestApp_Memory/executable.elf \ -Wl,-T -Wl,TestApp_Memory/src/TestApp_Memory_LinkScr.ld -g - I./ppc405_0/include/ -L./ppc405_0/lib/ \

TestApp_Memory/src/TestApp_Memory.c:39:19: xutil.h: No such file or directory make: *** [TestApp_Memory/executable.elf] Error 1

***************************************************************************

To solve this problem I use windows with the same system and I execute XPS->Software->generate libreries and BSPs. The files of /lib and / include are created

*************************************************************************** XPS INFO:

Configuring make for target include using: make -s include "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" Configuring make for target libs using: make -s libs "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" Compiling common powerpc-eabi-ar: creating ../../../lib/libxil.a Compiling bsp Compiling plb_arbiter Compiling opbarb Compiling uartlite Compiling cpu_ppc405 Libraries generated in \\storage\ferorcue\my_work\project\xps\xps_lin_v1_e\ppc405_0\lib\ directory Running execs_generate for OS'es, Drivers and Libraries ... LibGen Done. Created mapping for /xygdrive -> /cygdrive Done!

***************************************************************************

After that I can execute >Generate libraries and HDL files And >launch HDL simulator

In modelsim I compile the design by running the EDK compile script, Later I change the modelsim.ini to use the smartmodels. And I click s to simulate

s => load the design for simulation. (ModelSim 'vsim' # *** command with 'system') After loading the design, # *** set up signal displays (optional) and run the simulation. # *** (ModelSim 'run' command)

This is the error that I get :

*************************************************************************** XPS INFO:

s # vsim -t ps system_conf # ** Note: (vsim-3812) Design is being optimized... # ** Note: (vsim-3865) Due to PLI being present, full design access is being specified. # Loading /opt/modeltech/6.2a/linux/libswiftpli.sl # Loading /opt/modeltech/6.2a/linux/../std.standard # Loading /opt/modeltech/6.2a/linux/../ieee.std_logic_1164(body) # Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/ unisim/.vcomponents # Loading /opt/modeltech/6.2a/linux/../std.textio(body) # Loading /opt/modeltech/6.2a/linux/../ieee.vital_timing(body) # Loading /opt/modeltech/6.2a/linux/../ieee.vital_primitives(body) # Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/ unisim/.vpkg(body) # Loading work.system_conf#1 # Loading work.system(structure)#1 # Loading work.ppc405_0_wrapper(structure)#1 # Loading ppc405_virtex4_v1_01_a.ppc405_virtex4(structure)#1 # Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/ unisim/.ppc405_adv(ppc405_adv_v) # Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/ unisim/.ppc405_adv_swift_bus(ppc405_adv_swift_bus_v) # Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/ unisim/.ppc405_adv_swift(smartmodel) # Loading /opt/modeltech/6.2a/linux/libsm.sl # ** Note (SmartModel): # Copyright (c) 1984-2007 Synopsys Inc. ALL RIGHTS RESERVED # ** Note (SmartModel): # Platform Type: x86_linux (32-bit). # ** Note (SmartModel): # You can use the Browser tool to configure the SmartModel # Library and access information about SmartModels: # $LMC_HOME/bin/sl_browser # # SmartModel product documentation is available here: # $LMC_HOME/doc/smartmodel/manuals/intro.pdf #

formatting link
# # Notice: timing checks disabled with +notimingcheck at compile-time # Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/ unisim/.fpga_startup_virtex4(fpga_startup_virtex4_v) # Loading work.jtagppc_0_wrapper(structure) # Loading jtagppc_cntlr_v2_00_a.jtagppc_cntlr(structure) # Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/ unisim/.jtagppc(jtagppc_v) # Loading work.reset_block_wrapper(structure)#1 # Loading /opt/modeltech/6.2a/linux/../ieee.std_logic_arith(body) # Loading proc_sys_reset_v1_00_a.proc_sys_reset(imp)#1 # Loading proc_sys_reset_v1_00_a.upcnt_n(imp)#1 # Loading proc_sys_reset_v1_00_a.lpf(imp)#1 # Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/ unisim/.srl16(srl16_v) # Loading proc_sys_reset_v1_00_a.sequence(imp)#1 # Loading proc_sys_reset_v1_00_a.upcnt_n(imp)#2 # Loading work.plb_wrapper(structure)#1 # Loading plb_v34_v1_02_a.plb_v34(simulation)#1 # Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/ unisim/.fds(fds_v)#1 # Loading plb_v34_v1_02_a.plb_addrpath(implementation)#1 # Loading proc_common_v1_00_b.mux_onehot(imp)#1 # Loading proc_common_v1_00_b.mux_onehot(imp)#2 # Loading proc_common_v1_00_b.mux_onehot(imp)#3 # Loading proc_common_v1_00_b.mux_onehot(imp)#4 # Loading proc_common_v1_00_b.mux_onehot(imp)#5 # Loading proc_common_v1_00_b.mux_onehot(imp)#6 # Loading plb_v34_v1_02_a.plb_wr_datapath(simulation)#1 # Loading proc_common_v1_00_b.mux_onehot(imp)#7 # Loading plb_v34_v1_02_a.plb_rd_datapath(simulation)#1 # Loading plb_v34_v1_02_a.plb_slave_ors(implementation)#1 # Loading /opt/modeltech/6.2a/linux/../ieee.std_logic_unsigned(body) # Loading proc_common_v1_00_b.or_gate(imp)#1 # Loading proc_common_v1_00_b.or_gate(imp)#2 # Loading proc_common_v1_00_b.or_gate(imp)#3 # Loading proc_common_v1_00_b.or_gate(imp)#4 # Loading proc_common_v1_00_b.proc_common_pkg(body) # Loading /opt/modeltech/6.2a/linux/../synopsys.attributes # Loading /opt/modeltech/6.2a/linux/../ieee.std_logic_misc(body) # Loading plb_v34_v1_02_a.plb_arbiter_logic(implementation)#1 # Loading plb_v34_v1_02_a.plb_priority_encoder(simulation)#1 # Loading plb_v34_v1_02_a.priority_encoder(simulation) # Loading plb_v34_v1_02_a.qual_request(simulation) # Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/ unisim/.muxcy(muxcy_v) # Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/ unisim/.lut4(lut4_v) # Loading plb_v34_v1_02_a.pending_priority(simulation)#1 # Loading plb_v34_v1_02_a.qual_priority(qual_priority) # Loading plb_v34_v1_02_a.pend_request(simulation)#1 # Loading plb_v34_v1_02_a.arb_addr_sel(simulation)#1 # Loading plb_v34_v1_02_a.arb_control_sm(simulation)#1 # Loading plb_v34_v1_02_a.gen_qual_req(simulation)#1 # Loading plb_v34_v1_02_a.muxed_signals(implementation)#1 # Loading proc_common_v1_00_b.or_bits(implementation) # Loading plb_v34_v1_02_a.arb_registers(simulation)#1 # Loading plb_v34_v1_02_a.bus_control(simulation) # Loading plb_v34_v1_02_a.watchdog_timer(simulation)#1 # Loading proc_common_v1_00_b.down_counter(simulation)#1 # Loading plb_v34_v1_02_a.plb_interrupt(plb_interrupt)#1 # Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/ unisim/.fdre(fdre_v)#1 # Loading plb_v34_v1_02_a.bus_lock_sm(implementation) # Loading work.opb_wrapper(structure)#1 # Loading /opt/modeltech/6.2a/linux/../ieee.std_logic_signed(body) # Loading proc_utils_v1_00_a.conv_funs_pkg(body) # Loading opb_arbiter_v1_02_e.opb_arb_pkg(body) # Loading opb_v20_v1_10_c.opb_v20(imp)#1 # Loading opb_arbiter_v1_02_e.or_gate(imp)#1 # ** Fatal: (vsim-3348) Port size (1) does not match actual size (32) for port '/system/opb/opb/opb_abus_i/y'. # Time: 0 ps Iteration: 0 Instance: /system/opb/opb/opb_abus_i File: /opt/xilinx/EDK8.2/hw/XilinxProcessorIPLib/pcores/ opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd Line: 125 # FATAL ERROR while loading design # Error loading design

Do you know why "gmake" is not working?

Windows uses "make" and it compiles the libraries, but later It should work. Why I have a problem with a ip core from Xilinx (opb_arbiter_v1_02_e).

Do you think, that if I get the "gmake" working in Solaris it will compile the libraries in a different way and the simulation will work?

Thank you for your consideration

Reply to
ferorcue
Loading thread data ...

You seem to be missing gmake on SOL. This is typically available in /usr/local/bin/gmake

Perhaps you don't have /usr/local/bin in your $PATH Do "whereis gmake" to locate it on SOL.

Compling the elf file on either WIN or SOL would not matter since you are compiling for the target powerpc405 and not the development platform. So long as you have same sources and versions EDK tools on both WIN and SOL, then you should have the same ELF.

C> Hi friends,

Reply to
Paulo Dutra

I have a question:

I think that gmake is not installed in my operating system (solaris)

gmake:

whereas make is intalled

make: /usr/bin/make /usr/X11R6/bin/make /usr/bin/X11/make /usr/share/man/man1/make.1.gz

What file and how should I change in order to use make with LIBGEN ?

Thank you for your consideration.

Best regards Fernando Ortiz Cuesta

Reply to
ferorcue

I have a question:

I think that gmake is not installed in my operating system (solaris)

gmake:

whereas make is intalled

make: /usr/bin/make /usr/X11R6/bin/make /usr/bin/X11/make /usr/share/man/man1/make.1.gz

What file and how should I change in order to use make with LIBGEN ?

Thank you for your consideration.

Reply to
ferorcue

My supervisor installed gmake. The first problem is solved but not the second: In modelsim, when try to simulate (behavioral) it tries to load the whole system but the next massage is shown:

Loading opb_arbiter_v1_02_e.or_gate(imp)#1 # ** Fatal: (vsim-3348) Port size (1) does not match actual size (32) for port '/system/opb/opb/opb_abus_i/y'. # Time: 0 ps Iteration: 0 Instance: /system/opb/opb/opb_abus_i File: /opt/xilinx/EDK8.2/hw/XilinxProcessorIPLib/pcores/ opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd Line: 125 # FATAL ERROR while loading design # Error loading design

Someone have any idea?

gmake

Reply to
ferorcue

Hallo,

I have same problem and no solution for that. I have looked around whole Internet but with no effect.

The problem comes also during EDK 8.2 PowerPC Tutorial in Virtex-4 journey that is supposed to be bug free. Is not it?

Because I am going to operate with APU/FCM, the simulation feature is higly necessary for me!

Do you have any idea how to solve the problem please?

Thank for answer Jan Krakora

Reply to
CTU FEE Jan Krakora

To specify the problem, I thought the "Fatal: (vsim-3348)" one. Sorry Jan

Reply to
CTU FEE Jan Krakora

hi Jan,

I still have the problem. I am using linux (debian) and the people from xilinx told me today, that debian it is not supported, Only Red Hat Enterprise 3. But this is very weird because I am using it, and it works normally, the only think that is not working is the simulation in modelsim.

I told one of my supervisors and he told me that he thinks that our problem is not a problem of operating system or EDK, he thinks that it is a problem of Modelsim. But I dont know how to solve it.

I will continue trying to solve the problem, if you get a solution, please let me know

Reply to
ferorcue

Hi,

This message does not seem to be OS specific just as your supervisor said. I would bring it up again with the Xilinx tech support and ask them to try to reproduce it on their RH machine and if it is reproducible, then it is no longer OS specific. Everything I can see from the message makes it sound like it has to do with the EDK IP and not to do with the OS it is being run on.

Thanks Duth

Reply to
Duth

Hi fellows,

no, the problem is not OS specific, because I'm using Windows XP system (due to USB cable, not working under any Linux system). I think the problem is in the simulation IP cores used by ModelSim tool. I think we should inquire of Xilinx corp. after the problem to be solved, as soon as better.

I have also tried to change the OPB core revision to the depricated version

1.10b (older version of 1.10c, the default one), but Modelsim refused me with any warnings and errors. I will analyse it, we will see.

Stay in touch Regards Jan

Reply to
CTU FEE Jan Krakora

to USB cable, not working under any Linux system). I think the problem is in the simulation IP cores used by ModelSim tool. I think we should inquire of Xilinx corp. after the problem to be solved, as soon as better.

1.10b (older version of 1.10c, the default one), but Modelsim refused me with any warnings and errors. I will analyse it, we will see.

Hi friends,

I think that I have the solution, I found it in a xilinx webcase. in system_setup.do change: "vsim -novopt -t ps system_conf; set xcmds 1;"

Source:

9.1i EDK ModelSim - Error message: "logic.vhd(359): (vopt-1144) Value 0 is out of std.standard.natural range 1 to 32" 04/24/07 11:14:13

Problem Description:

Keywords: optimization, -vopt, -novopt

I am trying to simulate my EDK system. When I run the simulation in ModelSim 6.2b, I receive an error message similar to the following during the optimization phase:

"Error Message:

---------------------------------------

D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/hdl/vhdl/ opb_v20. vhd(550): (vopt-1144) Value 0 is out of std.standard.natural range 1 to

  1. # ** Error: D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/ park _lock_logic.vhd(359): (vopt-1144) Value 0 is out of std.standard.natural range 1 to 32. # ** Error: D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/ park _lock_logic.vhd(429): (vopt-1144) Value 0 is out of std.standard.natural range 1 to 32. # Optimization failed # Error loading design # Error: Error loading design # Pausing macro execution"

I was able to simulate this same design using a previous version of ModelSim (for example, 6.0a and 6.2a). The previous version of ModelSim did not include this optimization phase. What could be the problem? Solution 1: The problem is that in the later version of ModelSim, it is automatically inserting the -vopt command by default, which clashes with the EDK IP files for the EDK cores. This command performs global optimization on Verilog and mixed-HDL designs after they are compiled, which is not necessary for the EDK IP models.

You can work around this issue by inserting the -novopt command in the "do file" that you are using to run the simulation. Alternatively, you can work around this issue by setting the "modelsim.ini" variable "VoptFlow" to 0 (zero). The "modelsim.ini" files are located in the c: \\, c:\ and c: \ directories

Reply to
ferorcue

to USB cable, not working under any Linux system). I think the problem is in thesimulationIP cores used by ModelSim tool. I think we should inquire ofXilinxcorp. after the problem to be solved, as soon as better.

1.10b (older version of 1.10c, the default one), but Modelsim refused me with any warnings and errors. I will analyse it, we will see.

Hi,

Please send this information to Mentor Grpahics. They implemented vopt by default in order to improve simulation performance, although that does mean that it works seamlessly. Mentor is very keen on fixing all issues that have to do with vopt, so please send them this feedback so that you no longer have to use the -novopt switch. Using the simulator in default should be the ideal solution and all problems with the optimizer should be addressed.

Thanks Duth

Reply to
Duth

Hi folks,

I have not tested your recommended procedure yet. I have reinstaled the ModelSim to the older, recommended revision 6.1e and it works.

I followed "Introduction" section in "EDK Concepts, Tools, and Techniques" Xilinx article. It well describes what shoud be done step-by-step.

It works, and I am happy ;) Have a nice day Jan

Reply to
Jan Krakora

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