Hi,
I'm using PLB to read and write 64bit data through burst transactions. I can read and write data correctly, but watching the signals through chipscope I can see a strange behavior: the PLB_MWrDAck and PLB_MRdDAck don't occur in consecutive clock cycles. For instance, during a 16 words burst read, instead of taking 16 clock cycles to read all data after the bus has been granted to my peripheral, it takes about 190 clock cycles. Did anyone have the same problem??
Thanks,
Lucio Rech
PLB burst can indeed read/write in consecutive clock cycles. Perhaps your peripheral can't supply data fast enough? Assuming Xilinx ppc, the cache only reads/write 4 cycles (8 words) at a time.
Alan Nishioka
Hi,
I'm reading/writing directly from the DDR, so this can't be the problem. The peripheral is also using the highest priority and I double checked the signals, they are exactly how the IBM's Guide say.
Lucio Rech
But you still have not supplied enough information. What is on both sides of the bus transfer? Is one side your own custom peripheral? Are you trying to use IPIF? What speed are you running the bus? What chip are you using? Where in the world is Carmen Sandiego?
Alan Nishioka
Well, I don't think I can answer the last question, so let's move to the others :) What I am trying to do is a 64bit burst transfer with variable length between my peripheral and a DDRAM, both connected to the PLB Bus (the memory uses the plb_ddr v2.00a). I'm stimulating the bus myself, thus not using the IPIF. The bus runs at 100 MHz and I'm using a Virtex2 Pro (XC2VP30).
Lucio Rech
Well, I don't think I can answer the last question, so let's move to the others :) What I am trying to do is a 64bit burst transfer with variable length between my peripheral and a DDRAM, both connected to the PLB Bus (the memory uses the plb_ddr v2.00a). I'm stimulating the bus myself, thus not using the IPIF. The bus runs at 100 MHz and I'm using a Virtex2 Pro (XC2VP30).
Lucio Rech
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