Hi everyone!
I'm new to the group and quite a beginner in FPGA business. I have this very general question on BSDL files and JTAG - is there any possibility to include any internal signal (not connected directly to the output pin) in the scan register?
Chris
There is a primitive you can use to get JTAG access. See for instance the BSCAN_SPARTAN3 library element. You should find similar primitives for different families. Some folks on this newsgroup have utilized those primitives for more than just ChipscopePro (Xilinx) or Identify (Synplicity)debugging.
- John_H
Yes, there is documentation on the Xilinx site about how to do it and also many previous posts on this very newsgroup about it. Think BSCAN.
---Matthew Hicks
and there is VHDL source code of the BSCAN primitive as well
Antti
Thank you all very much, that's really helpful!
Chris
I've a question concerning BSCAN_SPARTAN3 primitive - since it adds "virtual" cell to the boundary scan register, do I have to include it somehow in the BSDL file, that describes the Boundary Scan Register of my chip?
Chris
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