Hi All, I have developed a design which obtained max freq. 56Mhz. So i applied global clock constraint to implement design and timimg is met. This design has sub-modules which are running above 100Mhz. my requirement is run this design at 90Mhz. when i applied global clock constraint for 90Mhz, then timing is not met. Finally i downloaded this design on board and see that design is working at 90Mhz. My question why tool is not meeting timing but design is working at board. I am not included false and multi-cycle path in design constraint file .
Design running on board but timing are not met
May 23, 2007
2 Replies
If a tool states a max frequency, this frequency has to be valid for worst case scenario. This means usually min voltage, max temperature and worst case silicon (and maybe some derating factors for ageing effects). Your design will run much faster with a device from a "good" waver run on max voltage and min temperature at the begining of its lifetime.
The next point is, that the max frequency may be determined by a few paths wich are seldom used. You might have a good time with overclocking until you need the longest path in the design. E.g. your longest path is the ripple carry of an adder which is the only path real exceeding the clock periode. This adder will do a good job until the day you have the full ripple over all bits. This adder will result n+1 for each increment of n except when n = max(n)/2.
bye Thomas
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