Hi All, I have developed a design which obtained max freq. 56Mhz. So i applied global clock constraint to implement design and timimg is met. This design has sub-modules which are running above 100Mhz. my requirement is run this design at 90Mhz. when i applied global clock constraint for 90Mhz, then timing is not met. Finally i downloaded this design on board and see that design is working at 90Mhz. My question why tool is not meeting timing but design is working at board. I am not included false and multi-cycle path in design constraint file .
- posted
16 years ago