Hi guys, To know how the synthesizer behave,i wrote logic to add 4 vectors in three different ways.And i got differnet result from the synthesizer(used both ISE and synplify). These are the three different approchs i made
1.*************************************************************************************************** module add( input clk, input [1:0] a,b, input d, input [63:0] c, output reg [64:0] out );reg [1:0] in1,in2; reg in4; reg [63:0] in3; wire [64:0] result;
always @ (posedge clk) begin {in1,in2,in3,in4}= {a,b,c,d}; out= result; end assign result= in1+in2+in3+in4;
endmodule
2.*************************************************************************************************** module add1( input clk, input [1:0] a,b, input d, input [63:0] c, output reg [64:0] out );reg [1:0] in1,in2; reg in4; reg [63:0] in3; wire [64:0] temp; wire [64:0] temp2; wire [64:0] result;
always @ (posedge clk) begin {in1,in2,in3,in4}= {a,b,c,d}; out= result; end
assign temp= in1+in2; assign temp2= temp+in4; assign result= temp2+in3;
endmodule
3.*************************************************************************************************** module add2( input clk, input d, input [1:0] a,b, input [63:0] c, output reg [64:0] out );reg [1:0] in1,in2; reg in4; reg [63:0] in3; reg [64:0] result;
always @ (posedge clk) begin {in1,in2,in3,in4}= {a,b,c,d}; out= result; end always @ (*) begin case({in4,in1,in2})
5'b00000: result= in3+3'b000; 5'b00001: result= in3+3'b001; 5'b00010: result= in3+3'b010; 5'b00011: result= in3+3'b011; 5'b00100: result= in3+3'b001; 5'b00101: result= in3+3'b010; 5'b00110: result= in3+3'b011; 5'b00111: result= in3+3'b100; 5'b01000: result= in3+3'b010; 5'b01001: result= in3+3'b011; 5'b01010: result= in3+3'b100; 5'b01011: result= in3+3'b101; 5'b01100: result= in3+3'b011; 5'b01101: result= in3+3'b100; 5'b01110: result= in3+3'b101; 5'b01111: result= in3+3'b110;5'b10000: result= in3+3'b001;
5'b10001: result= in3+3'b010; 5'b10010: result= in3+3'b011; 5'b10011: result= in3+3'b100; 5'b10100: result= in3+3'b010; 5'b10101: result= in3+3'b011; 5'b10110: result= in3+3'b100; 5'b10111: result= in3+3'b101; 5'b11000: result= in3+3'b011; 5'b11001: result= in3+3'b100; 5'b11010: result= in3+3'b101; 5'b11011: result= in3+3'b110; 5'b11100: result= in3+3'b100; 5'b11101: result= in3+3'b101; 5'b11110: result= in3+3'b110; 5'b11111: result= in3+3'b111;endcase end
endmodule
And the results for these from the ISE are
1.*************************************************************************************************** Selected Device : 4vlx15sf363-12Number of Slices: 105 out of 6144 1% Number of Slice Flip Flops: 134 out of 12288 1% Number of 4 input LUTs: 128 out of 12288 1% Number of bonded IOBs: 135 out of 240 56% Number of GCLKs: 1 out of 32 3%
Minimum period: 5.212ns (Maximum Frequency: 191.872MHz) Minimum input arrival time before clock: 1.445ns Maximum output required time after clock: 3.921ns Maximum combinational path delay: No path found
2.*************************************************************************************************** Selected Device : 4vlx15sf363-12Number of Slices: 76 out of 6144 1% Number of Slice Flip Flops: 134 out of 12288 1% Number of 4 input LUTs: 72 out of 12288 0% Number of bonded IOBs: 135 out of 240 56% Number of GCLKs: 1 out of 32 3%
Minimum period: 4.793ns (Maximum Frequency: 208.616MHz) Minimum input arrival time before clock: 1.445ns Maximum output required time after clock: 3.921ns Maximum combinational path delay: No path found
3.*************************************************************************************************** Selected Device : 4vlx15sf363-12Number of Slices: 712 out of 6144 11% Number of Slice Flip Flops: 135 out of 12288 1% Number of 4 input LUTs: 1329 out of 12288 10% Number of bonded IOBs: 135 out of 240 56% Number of GCLKs: 1 out of 32 3%
Minimum period: 6.377ns (Maximum Frequency: 156.803MHz) Minimum input arrival time before clock: 1.459ns Maximum output required time after clock: 3.921ns Maximum combinational path delay: No path found
*****************************And the Result from the Synplify are***************************************************************** 1.*************************************************************************************************** Mapping to part: xc4vlx15sf363-10 Cell usage: FD 134 uses GND 1 use MUXCY 1 use MUXCY_L 127 uses XORCY 128 uses LUT1 125 uses LUT2 4 usesMapping Summary: Total LUTs: 129 (1%)
----------------------------------------------------------------------------------------------------------------------- add|clk 1.0 MHz 143.8 MHz 1000.000
6.952 993.048 inferred Inferred_clkgroup_0 ======================================================================================================================= 2.*************************************************************************************************** Mapping to part: xc4vlx15sf363-10 Cell usage: FD 134 uses GND 1 use MUXCY 1 use MUXCY_L 127 uses XORCY 128 uses LUT1 125 uses LUT2 4 usesMapping Summary: Total LUTs: 129 (1%)
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------- add1|clk 1.0 MHz 143.8 MHz 1000.000
6.952 993.048 inferred Inferred_clkgroup_0 ======================================================================================================================= 3.*************************************************************************************************** Mapping to part: xc4vlx15sf363-10 Cell usage: FD 134 uses GND 1 use MULT_AND 2 uses MUXCY 1 use MUXCY_L 63 uses VCC 1 use XORCY 63 uses LUT1 61 uses LUT2 1 use LUT3 3 uses LUT4 2 usesGlobal Clock Buffers: 1 of 32 (3%)
----------------------------------------------------------------------------------------------------------------------- add2|clk 1.0 MHz 139.9 MHz 1000.000
7.146 992.854 inferred Inferred_clkgroup_0Can any one please help me why i am getting this much difference in the result and what should be the real approch to write in HDL to get most optimised result. Thanks in advance