Field-Programmable Gate Arrays

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How the synthesizer acutally works.

Hi guys, To know how the synthesizer behave,i wrote logic to add 4 vectors in three different ways.And i got differnet...
13 comments posted 19yrs
posted by subin.82
13 comments posted 19yrs posted by subin.82

M-RAM allocation in Stratix EPS125B672C6

Hi , I am using Altera Quartus II version 4.0 . The EPS125 device has 138 M4K blocks 224 M512 blocks 2 number of 512K M...
2 comments posted 19yrs
posted by nandits11
2 comments posted 19yrs posted by nandits11

Design running on board but timing are not met

Hi All, I have developed a design which obtained max freq. 56Mhz. So i applied global clock constraint to implement des...
2 comments posted 19yrs
posted by jrgodara
2 comments posted 19yrs posted by jrgodara

LVCMOSS33 I/O sink current

I am using spartan3 fpga with lvcmos33 output pin set to 16 mA drive strength and fast slew rate. I am assuming that 16...
6 comments posted 19yrs
posted by cpandya
6 comments posted 19yrs posted by cpandya

JTAG FPGA Debugging

Hi everyone! I'm new to the group and quite a beginner in FPGA business. I have this very general question on BSDL file...
5 comments posted 19yrs
posted by K.Pisaniec
5 comments posted 19yrs posted by K.Pisaniec

how 33-bit BRAM?

Hi I need to implement 33-bit data BRAM. Obviously, following BRAM will not work. Does anyone suggest how to implement...
3 comments posted 19yrs
posted by pasacco
3 comments posted 19yrs posted by pasacco

ISE Service pack

For some reason i am not able to download ISE service pack for 9.1i version. Can any body upload it ?
1 comments posted 19yrs
posted by sudarshan.onkar
1 comments posted 19yrs posted by sudarshan.onkar

"black_box"-ing of components in toplevel

Hi again, What does the setting of the attribute box_type to "black_box" for my toplevel components effect (concerning...
3 comments posted 19yrs
posted by l.s.rockfan
3 comments posted 19yrs posted by l.s.rockfan

Problems to simulate (behavioural) in XPS

Hi friends, I am working with Solaris and with all the systems that i generate with XPS have the same problem. I have a...
12 comments posted 19yrs
posted by le_marq
12 comments posted 19yrs posted by le_marq

Problem with DDR2 controller

Hi to all I am currently working on DDR2 controller for Burst Lenth 8. My own code is giving good results when i verifi...
0 comments posted 19yrs
posted by sudhakarmvs
0 comments posted 19yrs posted by sudhakarmvs

PLB behaviours strangely during burst transactions

Hi, I'm using PLB to read and write 64bit data through burst transactions. I can read and write data correctly, but wat...
5 comments posted 19yrs
posted by luciorech
5 comments posted 19yrs posted by luciorech

PLB behaviors strangely during burst transactions

Hi, I'm using PLB to read and write 64bit data through burst transactions. I can read and write data correctly, but wat...
0 comments posted 19yrs
posted by luciorech
0 comments posted 19yrs posted by luciorech

using FPGA JTAG as GPIO

Hi I want to debug a custom board with no interface for data exchange. The requirement is PC based autometic test patte...
1 comments posted 19yrs
posted by moazzamhussain
1 comments posted 19yrs posted by moazzamhussain

DDR Controller Blue

Dear all, I am working on a DDR controller that stores captured video frames from which a VGA controller retrieves data...
5 comments posted 19yrs
posted by michaelmkliu
5 comments posted 19yrs posted by michaelmkliu