converting verilog to vhdl

For future reference this is called conditional assignment. Next time you can just google "VHDL conditional assignment".

---Matthew Hicks

module Reg2(Q, D, en, rst, clk);

parameter REGWIDTH = 2;

input clk, en, rst; input [(REGWIDTH-1):0] D; output [(REGWIDTH-1):0] Q;

reg [(REGWIDTH-1):0] Q_int;

assign Q = (rst == 0)? Q_int : 2'd0;

always @ (posedge clk) begin if (rst == 1) Q_int en_temp, D => D_temp, Q => Q_temp );

-- Passing values to inputs clk_temp

as

Remove the line:

Q(1 downto 0)

How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0;

if i remove Q(1 downto 0)

statement

Sorry, my bad. I read your code too quickly, and thought you wer assigning to Q in the clocked precess as well.

Try: Q(1 downto 0)

neither one works. I am still having the same problem

Could there be an issue with not having a "wait" at the bottom of your testbench process? Maybe that process is executing every delta cycle, with time never moving forward.

It maybe possible. Let me check on this and see what happens.

I'm not sure where you got the code, but it looks like it is a flop with a synchronous reset and enable, and then anding the output with reset after the register.

I would convert it as follows to a standard asynchronous reset circuit. The only difference in behavior would be if rst is high for less than a clock cycle, but not while the clock is actually rising (in which case the original circuit output would be 0 while rst, but return to whatever q_int was afterwards, whereas the new circuit will stay at 0 until something is clocked into q).

process (clk, rst) is begin if rst = '1' then q '0'); elsif rising_edge(clk) and (en = '1') then q

I cannot change the reset to ssynchronous. My employer wants it to be synchronous.

The wait statement did not help. I have clk_temp

I tried the solution you gave me. I am still having the same problem, Q or Q_int is still "00" at all time

I FOUND THE SOLUTION. INSTEAD OF USING TEMPORARY SIGNAL Q_INT, I DIRECTLY UPDATED THE VALUE OF OUTPUT Q. IT IS WORKING FINE NOW. Andys tip of not reassigning signals to itself really helped. Thanks everybody.