6 years ago
e your VHDL testbenches - and to make easily understandable, maintainable,
extendible and reusable testbench architectures.
UVVM is free and open source, and now a whole set of BFMs and Verification
Components are also available - open source and for free. This allows a ver
y fast kick-off for new users of UVVM, and of course a really good start fo
r any VHDL testbench development. They also serve as examples on how users
can make their own BFMs and VVCs. In fact - if you have already made your B
FM procedures for your proprietary protocol - you can make a VVC for that i
nterface in 15 to 60 minutes.
Spend 5 minutes to read our post
'Advanced VHDL Verification - Made simple - For anyone'
and see for your self how UVVM will
allow far better and more structured testbenches to be implemented far fas
ter than before.
(Includes picture, so can't be posted here)
UVVM is free and open source, and you can use it for anything you like, wit
h no restrictions other than the standard MIT open source license.
UVVM is available from github.com and bitvis.no (released in February 201
Note that advanced randomization and coverage is available with UVVM via th
e included OSVVM or adapted UVVM-OSVVM.
Available BFMs and VVCs (VHDL Verification Components) are:
- Avalon-MM (Single access so far)
- SBI: Simple Bus Interface (Single cycle, optional ready - very simple bus
- SPI (coming in June)
- GPIO (coming in June)
As UVVM takes off we expect the VHDL community will make more BFMs and VVCs