Latest threads in Field-Programmable Gate Arrays

Re: ANNC: FPGA Noise Fundamentals Webcast

Is there a text version? I've never understood the logic of listening to someone drone on in a thick foreign accent whe...

1 19yrs

MikeShepherd564

1 19yrs MikeShepherd564

tricking bitgen into creating rom-like behavior

Is there a way I can read in a text / ascii /binary file AFTER P&R is done to mimic a ROM ? I could use block-RAM inste...

4 19yrs

mittra

4 19yrs mittra

Null statement in VHDL

Hi, I rarely use null statement in my designs. I check the definition of null statement from book "HDL Chip Design" wri...

26 19yrs

wtxwtx

26 19yrs wtxwtx

bidirectional pin help

Hi everyone I am working on some FPGA project and I need to define one port as bidirectional. This is my VHDL code...

15 19yrs

Zorjak

15 19yrs Zorjak

Looking for VME-Bus Core

Hello, does anybody know a synthesizable VME-Bus Core. A few years ago there was a core outside there from silicore with...

0 19yrs

c.kirschenlohr

0 19yrs c.kirschenlohr

Partial reconfiguration using ICAP

HI all, I am trying to download Partial bit streams created by Planahead , through ICAP port.The Xilinx board i am usin...

4 19yrs

ajith.thamara

4 19yrs ajith.thamara

Newbie with ISE 9_2_02i_lin gets error : Process "Translate" failed

Downloaded ISE 9.2i day before yesterday. Installed t9_2_02i_lin update and am just going through the counter example i...

4 19yrs

usenet

4 19yrs usenet

[xilinx ise simulation] how to keep all settings between runs

Hi all Is there a way to keep the settings (specifically the format of signals, and the widht of the name and value col...

3 19yrs

bart

3 19yrs bart

Overriding a VHDL generic for command-line driven synthesis with ISE

Hi friends i have a question regarding ISE Webpack (7.1 to 9.1 versions): Is it possible to override the value of a VHD...

0 19yrs

nkavv

0 19yrs nkavv

A beginner asks questions about synthesis under Xilinx XST

I've realised there are many things I don't know about the synthesis process under Xilinx XST. The top level of code is...

2 19yrs

ethel.thefrog

2 19yrs ethel.thefrog

Implementing MIPS Memory Hiarchy

Hi there, I have a more general question about processor design, hope that is alright ;) I am just implementing some ki...

3 19yrs

Roman.Zeilinger

3 19yrs Roman.Zeilinger

hwicap for EDK 9.1

Hey guys & gals, I've been experiencing some difficulty using the opb_hwicap for EDK 9.1. I'm trying to use it for read...

0 19yrs

coolkev

0 19yrs coolkev

Dynamic power estimation using Xpower

Hi. I am using Xpower for estimating the total dynamic power consumption of my processor which is described in VHDL. I...

2 19yrs

mahshid.sedghy

2 19yrs mahshid.sedghy

Samtec PowerPoser power filtering solution.

http://www.samtec.com/sudden_service/current_literature/powerposer.asp I saw this and thought of comp.arch.fpga . I'm n...

4 19yrs

symon_brewer

4 19yrs symon_brewer

xilinx impact 9.2 problem

Hello out there, I don't know whether this is the right group to post this message. Still, I'll try anyway. For a few w...

6 19yrs

me

6 19yrs me

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