Field-Programmable Gate Arrays

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Null statement in VHDL

Hi, I rarely use null statement in my designs. I check the definition of null statement from book "HDL Chip Design" wri...
26 comments posted 18yrs
posted by wtxwtx
26 comments posted 18yrs posted by wtxwtx

bidirectional pin help

Hi everyone I am working on some FPGA project and I need to define one port as bidirectional. This is my VHDL code...
15 comments posted 18yrs
posted by Zorjak
15 comments posted 18yrs posted by Zorjak

Looking for VME-Bus Core

Hello, does anybody know a synthesizable VME-Bus Core. A few years ago there was a core outside there from silicore with...
0 comments posted 18yrs
posted by c.kirschenlohr
0 comments posted 18yrs posted by c.kirschenlohr

Partial reconfiguration using ICAP

HI all, I am trying to download Partial bit streams created by Planahead , through ICAP port.The Xilinx board i am usin...
4 comments posted 18yrs
posted by ajith.thamara
4 comments posted 18yrs posted by ajith.thamara

Implementing MIPS Memory Hiarchy

Hi there, I have a more general question about processor design, hope that is alright ;) I am just implementing some ki...
3 comments posted 18yrs
posted by Roman.Zeilinger
3 comments posted 18yrs posted by Roman.Zeilinger

hwicap for EDK 9.1

Hey guys & gals, I've been experiencing some difficulty using the opb_hwicap for EDK 9.1. I'm trying to use it for read...
0 comments posted 18yrs
posted by coolkev
0 comments posted 18yrs posted by coolkev

Dynamic power estimation using Xpower

Hi. I am using Xpower for estimating the total dynamic power consumption of my processor which is described in VHDL. I...
2 comments posted 18yrs
posted by mahshid.sedghy
2 comments posted 18yrs posted by mahshid.sedghy

Samtec PowerPoser power filtering solution.

http://www.samtec.com/sudden_service/current_literature/powerposer.asp I saw this and thought of comp.arch.fpga . I'm n...
4 comments posted 18yrs
posted by symon_brewer
4 comments posted 18yrs posted by symon_brewer

xilinx impact 9.2 problem

Hello out there, I don't know whether this is the right group to post this message. Still, I'll try anyway. For a few w...
6 comments posted 18yrs
posted by me
6 comments posted 18yrs posted by me

OCM BRAM and PCC issues...

Hello All, I am using Virtex II pro for a design with PPC,Timer, Bram, OCM, PLB,OPB. The Bram is attached on the OCM bu...
0 comments posted 18yrs
posted by lastval
0 comments posted 18yrs posted by lastval

DDR2 controller V4 vs V5 differences ?

Hi, I've been working on Virtex 4 with a DDR2 controller for about 1 year now and it works fine. The controller is base...
6 comments posted 18yrs
posted by SomeOne
6 comments posted 18yrs posted by SomeOne