Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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xil_printf and %u specifier
Hello all, I'm using EDK 9.1.02i to develop an application for the Xilinx University Program Virtex-II Pro board. I created a bare MicroBlaze project and ran the following program on it: #include int...
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16 years ago
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Xilinx Foundation 9.2 vhdl project won't run without executing cleanup project files
Once routed, project won't simulate (ModelSim) unless "cleanup project files" is executed. Once simulated, project won't translate, map, ppr, etc until "cleanup project files" is executed (the only...
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16 years ago
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FPGA quiz 1&2, we have the answers and winners
Hi thank you all for nice feedback and suggestion, for both posted FPGA- quiz's the accepted answers have been posted. Both WINNERs will receive a FPGA miniconsole from Xiltendo a photo from the very...
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16 years ago
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High level FPGA work flow: available tool?
Hello everyone, in our company we're using FPGA Advantage of Mentor Graphics to develop FPGA design. The Boss ask for an "higher level" work flow than RTL level. Do someone give me some information...
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16 years ago
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IPs in MHS file
Hello all:) I am running a design in edk 6.1 version. and comes up with " Makefile cannot be saved to run process. Please ensure IPs in MHS file point to the right MPDs". The MHS doesnt contain info...
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16 years ago
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gold code - seed value
Hi, I'm trying to generate in hardware the set of all gold codes derived from two m-sequences. I'm having a hard time finding pointers as to how to change the seed of one LFSR with respect to the...
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16 years ago
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ethernet phy or mac
Hi Does anyone have any experiences with connecting a MAC rather than a PHY to a spartan(3e). I don't know yet whether to use a microblaze or my own state machine to connect to the ethernet. For...
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16 years ago
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FPGA to FPGA Bus
Hi I would like to connect 3 FPGA devices together using a 32-bit bus. Also would like all 3 to be masters on the bus. Is there any standard bus ou there that would do this rather than me coming up...
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16 years ago
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RTM ERROR:fail to get the remote thread list.
when Debug in NIOS II,,the waring message is :RTM ERROR:fail to get the remote thread list.. why?
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16 years ago
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Xilinx:is it possible to install Impact 9.1only?
Hi,in a previous post i asked about an easy way to have my fpga self programmed at power on Xapp 974 shows how to program a SPI Flash with Impact 9.1.,it looks like a very simple method My freeware...
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16 years ago
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FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2
Hi folks, the answers the first quiz have made some smile to my face, so I decided to make it more interesting and am actually offering prizes for the first correct answer, prizes will be FPGA...
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16 years ago
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Xilinx FIFO Flag Question
I generated a 32-bit by 1024 entry FIFO using the FIFO Generator. The FIFO is an independently-clocked BRAM that has a 39 MHz clock on the write side and a 100 MHz clock on the read side. I am writing...
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16 years ago
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Xilinx timing constraints incorrect?
Hello all, I am working on a design for a Xilinx V2P50 and I am trying to diagnose possible timing issues because the hardware performance of my design does not appear to match simulation. I have run...
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16 years ago
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FPGA quiz: what can be wrong
vhdl code LED1
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16 years ago
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profiling in modelsim
Hi, Iam working on profiling , using 6.1d version, memory profiling reports generated for my project code is interims of mega bytes(total memory allocated) . when I run same project code on the...
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16 years ago
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