Field-Programmable Gate Arrays

mess around with supply voltage to cyclone III

Hi, I have a Cyclone III FPGA. I have created a circuit on it whose performance I want to observe under the influence o...

2 comments posted 18yrs

posted by fpgazone

2 comments posted 18yrs posted by fpgazone

Re: Wishbone Specification in Action

> > Anyone with an example of how the specification can be translated into > implementation? > > Thanks! > http://www.op...

0 comments posted 18yrs

posted by symon_brewer

0 comments posted 18yrs posted by symon_brewer

Error using SOPC builder - "Custom SDRAM" with 8-bits gives error with Signal "az_be_n"

I'm trying to make a SDRAM controller with SOPC builder, but when I change the data width to 8bits I get the following...

1 comments posted 18yrs

posted by sendthis

1 comments posted 18yrs posted by sendthis

Fast Sampling of digital signals

Hi, I'm building a S/PDIF Receiver for implementation on spartan 3 fpga. I don't have an expensive DSO to analyze the s...

7 comments posted 18yrs

posted by aramosfet

7 comments posted 18yrs posted by aramosfet

FPGA pin swapping utility

We are using V5LX110T and V5L330 FPGAs. Are there decent pin swapping utilities so that we do not have to spend a lot o...

6 comments posted 18yrs

posted by cpandya

6 comments posted 18yrs posted by cpandya

VHDL trivia?

Hi folks! A bit of VHDL trivia. What I want is the reverse of: one_hot_gen: for i in 0 to 15 generate begin one_hot(i)

15 comments posted 18yrs

posted by phq

15 comments posted 18yrs posted by phq

Dynamic Reconfiguration books

Hi everybody! I would like to get advises about good books in dynamic reconfiguration using FPGAs. I need theoretical (a...

7 comments posted 18yrs

posted by taileb.mehdi

7 comments posted 18yrs posted by taileb.mehdi

xilinx Edititons

Hello all, I would like to ask if i can install in my computer 2 different versions of EDK, one older than the other. O/...

4 comments posted 18yrs

posted by lastval

4 comments posted 18yrs posted by lastval

What to consider for source synchronous clocking?

Hi everyone, pardon me but I'm pretty new to this. I'm using a Spartan 3 right now, and I'm trying to provide source sy...

3 comments posted 18yrs

posted by leowyuan

3 comments posted 18yrs posted by leowyuan

systemc thread processes are called with the same thread in windows

i observed that all processes registered with SC_THREAD macro are called with the same thread. Is this correct? In my m...

0 comments posted 18yrs

posted by manusha

0 comments posted 18yrs posted by manusha

difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES

Hi alls, I've a question which seems stupid, but I don't find answer anywhere.. ( maybe I don't search correctly ) What...

6 comments posted 18yrs

posted by michel.talon

6 comments posted 18yrs posted by michel.talon

FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround

Hi ho here is code process (m_sck) begin if (m_sck'event and m_sck=3D'1') then do64(62 downto 0)

24 comments posted 18yrs

posted by Antti.Lukats

24 comments posted 18yrs posted by Antti.Lukats

Reason for LUT1_L buffer insertion in Synplify EDIFs?

When generating EDIF from Synplify, I frequently notice buffers (LUT1_L primitives with INIT property of 2) inserted in...

4 comments posted 18yrs

posted by neil.steiner

4 comments posted 18yrs posted by neil.steiner

xil_printf and %u specifier

Hello all, I'm using EDK 9.1.02i to develop an application for the Xilinx University Program Virtex-II Pro board. I cre...

2 comments posted 18yrs

posted by pgp

2 comments posted 18yrs posted by pgp

Xilinx Foundation 9.2 vhdl project won't run without executing cleanup project files

Once routed, project won't simulate (ModelSim) unless "cleanup project files" is executed. Once simulated, project won'...

0 comments posted 18yrs

posted by danielgkNOSPAM

0 comments posted 18yrs posted by danielgkNOSPAM