FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2

Delays in the JTAG chain that shift the data by 1 bit ? Was the JTAGID manufacturer field still the Xilinx ID ?

Laurent Pinchart

JTAG ID returned vendor Xilinx family Virtex-II device 0 (invalid)

this same (wrong!) JTAGID returned all the time

TDO driven by more than one component ? If two Xilinx parts drive TDO in sync (instead of being properly chained) conflicts will occur for the family and device ID by not the vendor ID.

Laurent Pinchart

single IC chain

Antti (sorry for posting from different account, google goups asserted temp. block on my primary account)

Could the family and device ID be stored as some kind of fuses that got burnt when VCCINT was raised to 1.8V ?

Laurent Pinchart

it was my first guess too, but no this is not the case

Antti

Is this the Spartan 3A that was originally going to be a Virtex family chip, then they rebranded it but did not change the ID?

S Woods

Did the JTAGID change after you applied VCCINT=1.8V or was it already defective before ?

Laurent Pinchart

I did not observe the wrong ID before. I did some rework on the PCB, the VCCINT regulator VCCADJ did fell off, and i was suddenly measuring 1.8V after fixing the supply and completing my PCB rework, the ID was wrong.

the problem has been fixed, and the same FPGA now works fully ok again and returns correct ID too.

Antti

JTAGID

WAU, thats good guess!!

well on the plastic housing there is part of the text that has been laser-erased after chip marking for some reason

but no, this is not the case for the wrong ID readback

Antti

Single IC chain, but is there more than one entity on the chain, say a V2 before/after it. If so, the spartan could have stuck itself in constant pass-through and the other device was the only one responding on the chain.

-- Mike

single chain, single TAP entity in the chain

Antti

Is it possible that voltage feed for the ID code is sourced from two different locations inside the FPGA and that the first part of the ID is generated properly but the latter becomes erased/garbled?

JTAGID

in

Recheck decoupling capacitors and power destribution on the board. if you want to avoid this error, assign boundary scan descriptive language file (of spartan 3A) to FPGA in IMPACT.

Hope it won't help.... :-), but i solved my problem this way.

MH

JTAGID

TDO in

text -

And yes, I forgot, change the computer or reintall Windows, (if you are using it)......... A logical solution to an illogical problem....

JTAGID

TDO in

text -

and we have another WINNER, I think this answer should already accepted.

I have not been able to fix the problem by adding bypass caps, but the issue is:

"100MHz noise on VCCINT". a canned oscillator is generating extreme noise that seems to pass all bypass caps..

so what it looks: when supply connected to VCCINT regulator drops, so that VCCINT also drops, then

VCCINT > 1.17V bad ID