Field-Programmable Gate Arrays

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XPS FIFO PLB device problems... (verilog)

Hi all, I'm trying to develop a core that is connected to the PLB bus and uses FIFO to communicate to the PPC. The FPGA...
0 comments posted 18yrs
posted by andrea.pellegrini
0 comments posted 18yrs posted by andrea.pellegrini

Which demo board

Hello all, I need to develop a broadcast application using FPGA, but I am new to FPGA. I thus consider buying a demo bo...
0 comments posted 18yrs
posted by invalid
0 comments posted 18yrs posted by invalid

Nios II, ThreadX, NetX Anyone?

Hi, I'm looking for a very compact TCP/IP stack for the Nios II, and the ThreadX/NetX combo seems to be, at least on pa...
4 comments posted 18yrs
posted by paulspamdotkinzerspam
4 comments posted 18yrs posted by paulspamdotkinzerspam

Nios II, ThreadX, NetX

Hi, I'm looking for a very compact TCP/IP stack for the Nios II, and the ThreadX/NetX combo seems to be, at least on pa...
2 comments posted 18yrs
posted by paulspam.kinzerspam.spam.spam.spam
2 comments posted 18yrs posted by paulspam.kinzerspam.spam.spam.spam

Changing refresh rate for DRAM while in operation?

Hi, I'm trying to control a SDR SDRAM (Micron 64Mbit chip) using an Altera DE2 board. I've gotten the hardware interfac...
50 comments posted 18yrs
posted by sendthis
50 comments posted 18yrs posted by sendthis

Alter RBF Compression

Hi, Does anyone know which algorithm or scheme is used by Quartus to compress FPGA configuration files such as SOF or RB...
6 comments posted 18yrs
posted by jtang
6 comments posted 18yrs posted by jtang

ISE or EDK?

Hello, I want to design a system which includes ADC, digital filter, DAC with dataflow chart like this: audio_signal1->...
3 comments posted 18yrs
posted by vladimir.v.korostelev
3 comments posted 18yrs posted by vladimir.v.korostelev

microprocessor on fpga problems

Hi, Just wondering what could go wrong when synthesizing memories (i- cache, d-cache, and write buffer) of microprocesso...
7 comments posted 18yrs
posted by camwwang
7 comments posted 18yrs posted by camwwang

Building a Huffman codebook in VHDL

Hi, I've been looking at available VHDL/Verilog implementations of huffman coders. It appears that all currently availa...
3 comments posted 18yrs
posted by ennonymous
3 comments posted 18yrs posted by ennonymous

DVB-T/H help me ?

Hello, excuse me for my not perfect English. I must begin a project for the realization of the DVB-T/H modulator. I am...
0 comments posted 18yrs
posted by 78kappa78(at)virgilio(dot)it
0 comments posted 18yrs posted by 78kappa78(at)virgilio(dot)it

virtex-4 power consumption

Now I have ported a design from virtex-2 to virtex-4,because the xilinx announced virtex-4 have a lower dynamic power,b...
1 comments posted 18yrs
posted by sunry.zhang
1 comments posted 18yrs posted by sunry.zhang

Files produced by Quartus II compiler

Hi, I'm a student using Altera Quartus II v6.1 to program a Cyclone II on a DE2 development board. I'm starting to buil...
3 comments posted 18yrs
posted by allanlewis99
3 comments posted 18yrs posted by allanlewis99

LEDs, buttons and LCD

Hello folk! Hello, I have just bought Spartan 3E-1600E Microblaze Development kit and I am complete beginner. Really wa...
8 comments posted 18yrs
posted by vladimir.v.korostelev
8 comments posted 18yrs posted by vladimir.v.korostelev

FPGA input level conversion

+----------* +3,3V output --- | | R=66 ohm | | --- | ---- \ / CDBU00340 or similar Vf=0.6 \/ ---- | FPGA +2,5V input *-...
9 comments posted 18yrs
posted by pbFJqKD
9 comments posted 18yrs posted by pbFJqKD