vhdl code
LED1
vhdl code
LED1
incorrect ucf file had some other signals driving the pins?
LEDs are installed backwards and there is also maybe a short?
no. no pin mapping problem, no LED connection problems. if LED1 and LED 2 are driven from other signal they work properly. keep thinking;)
I solved the issue, but to avoig going nuts I called my wife to look the code too. then id take some break and slept over it. and finally solved.
Antti
Bad Power Supply? Ground loop or supply instability generating continuous powerup of you FPGA.
Bad VHDL coding? Description of asynchronous logic (latches).
Laurent
Antti wrote:
NO NO NO NO
waiting for more suggestions :)
Antti
if this is not the VHDL code, let us know the VHDL generating the some_signal and the blink_one_second.
the signal driving LED2 goes only to LED2, also no signals used to generate blink_one_second are in any way used in the part that generates some_signal, let say some_signal comes from external switch directly, and has no FPGA logic except routing.
Antti
I had a somewhat similar puzzle quite a few years ago. The code had a flip-flop generating out1 and an async assignment out2 = not out1. The two outputs were driving external buffers. Somehow the outputs got enabled together and the buffers smoked. I traced the problem to the synthesizer setting, which created another flop for the out2 and moved negation to its input. I don't remember all the details now, but IIRC the clock was missing for whatever reason when I first powered the board... Apparently debugging that board was my first assignment at a new job. Imagine how I felt when it smoked :)
/Mikhail
eh, but no one is getting closer to my issue. another hint, no flip flip or any sync logic thing is causing this problem. its also not in any way some compiler or P&R weirdness at all.
Antti
Did someone get too cheap in the board design and only use a single current limit resistor for both LEDs? If the blink LED has a significantly lower forward drop than the some_signal LED, then when blink LED turns on, it turns off some_signal LED, and when it goes off, some_signal LED comes back on. (You said they blink at the same time, but didn't mention polarity).
same blink rate, same polarity. but it was a good guess. and no it has nothing todo with the LED external wiring.
Antti
Are the IO bank VCCO's, IO types and LED drive levels properly matched up?
Elsewhere in your code, is some_signal or blink_one_second ever assigned the value 'Z'?
Hi Antti, Later on in your code you wrote:-
LED1
One of the LEDs was installed backwards?
I think you should explain how the LEDs are connected. I don't think what you are describing would be possible if the LEDs were connected through individual current-limiting resistors with their anodes to FPGA pins and with their cathodes to GND. Also, I assume no FPGA special-purpose pins are involved...
/Mikhail
Antti wrote: (...)
Hi Antti
I would suggest an incorrect mapping between the physical pins and the VHDL top-level ports (bad or missing UCF file).
Candidates are
-jg
DCI.
-- Phil Hays
weak/no internal pull-up/down on LED1? Drive current?
all IO types OK no Z involved
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