High level FPGA work flow: available tool?

Hi,

You should maybe start by the 58th Xcell Journal, dedicated to ESL tools.

good luck

csb

Thanks.

In Xcell Journal the proposed tool are "function-specific" or oriented to Hardware Acceleration.

I'm looking for a work flow to develop generel purpose FPGA function, starting from high level description.

For example I'd like to start from "C-model" or "MATLAB model" or "?!? model" and by using efficent compiler obtain a synthesizable RTL code.

I don't know this world (I always used VHDL or block diagram)...plese be patient!

thanks, thanks

There are a number of tools that operate in the ESL/synthesis space, however, you need a serious EDA budget to get any of these tools. In addition to this these tools are not general purpose and they normally operate well in a particular niche area (e.g. DSP/datapath). You already mentioned Catapult that can synthesize C/C++ to HDL (Verilog/ VHDL), other tools like Catalytic can convert M-Code to C, tools like SystemCrafters/ForteDS/BlueSpec/Agility/etc allow you to go from SystemC to HDL but as I mentioned, these tools are not cheap, work in a niche area and require specialist knowledge to drive them well.

Hans

It's easier to change your Boss than your toolset. Remind him or her of that from time to time.

Allan

Consider a change of style. Single process vhdl design entities:

-- Higher level C-like sequential description.

-- vendor independence

-- variables

-- functions

-- procedures

-- nothing to buy. Working synthesis examples here:

-- Mike Treseler

I was going to change my shirt, but I changed my mind instead. -- Winnie the Pooh ...

While it is possible to raise the level of abstraction using single processes, variables, functions, etc., the description must still be explicitly about what happens in each and every clock cycle. Even some simple cases of retiming can allow one to describe an operation that will take place over a specific number of clock cycles, but you have little or no control over the resulting division of the circuit across clock cycles.

Catapult and other C or matlab tools allow you to take an untimed (no clock cycles yet) algorithm and play around with parallelism and pipelining to alter the latency/throughput (and area/speed) of the implementation, without touching the C code (ok, some major changes require modifying the C code). They do this by presenting you with various views of the algorithm (resources, gant charts, etc.) and allow you to manipulate those views by adjusting parameters (at least that's how Catapult works). The really nice thing about it is they automagically generate the control logic for all the scheduling, multiplexing, etc.

That said, Catapult is clearly a datapath tool; it does not handle arbitrary control logic very well. But you can specify different types of interfaces (dual/single port memory, fifo, streaming, registers, etc.) and handshaking, and it will create and bolt that onto the algorithmic implementation for you.

Andy

Hi again,

why don't you have a look to AccelDSP Synthesis Tool, from Xilinx? of course it takes part of your budget, but it's easy to code in matlab at any description level

you have and interesting discussion on this topic in chapter 11, C/ C++ etc.-Based Design Flows of Clive Maxfield's "the design warriors guide to fpga's", it might be an article around, you can look for that using keywords

csb

That is the downside, but that is also the ticket to easy synthesis.

If I can't get n:=n+1; done in one clock cycle, I have to break up the variables and declare a counter or enumeration to update and case.

But I expect that an embedded C programmer who has written an interrupt routine would get it for control logic and simple math. It might even placate Maroc's boss :)

I agree that complicated DSP requires some sort of algorithm generator like matlab or Catapult (and thanks for the catapult tutorial by the way)

I don't see that as a downside as long as the simulation matches at the ports.

And this is where plain-old vhdl is more than good enough.

-- Mike Treseler

Maybe AutoPilot tool is cheaper ? It converts high-level C/C++/SystemC code to RTL.

see

P.