Hello all,
I am working on a design for a Xilinx V2P50 and I am trying to diagnose possible timing issues because the hardware performance of my design does not appear to match simulation.
I have run the design through Timing Analyzer (ISE 8.2) and notice a huge number of unconstrained paths of the following format
"FROM *clk_pad* TO *register*"
where *clk_pad* is a clock pad in the design, and *register* is a register in the design that is clocked. Am I missing a necessary timing constraint to eliminate these unconstrained paths? I have period constraints for all of the clocks in the design. If these paths are "correctly" unconstrained, is there any way to eliminate them from Timing Analyzer easily (preferably via command line, not in the GUI) so that only valuable unconstrained paths appear?
Thanks for all of your help.