Field-Programmable Gate Arrays

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FPGA quiz 1&2, we have the answers and winners

Hi thank you all for nice feedback and suggestion, for both posted FPGA- quiz's the accepted answers have been posted....
4 comments posted 18yrs
posted by Antti.Lukats
4 comments posted 18yrs posted by Antti.Lukats

High level FPGA work flow: available tool?

Hello everyone, in our company we're using FPGA Advantage of Mentor Graphics to develop FPGA design. The Boss ask for a...
9 comments posted 18yrs
posted by md2003
9 comments posted 18yrs posted by md2003

IPs in MHS file

Hello all:) I am running a design in edk 6.1 version. and comes up with " Makefile cannot be saved to run process. Plea...
2 comments posted 18yrs
posted by lastval
2 comments posted 18yrs posted by lastval

gold code - seed value

Hi, I'm trying to generate in hardware the set of all gold codes derived from two m-sequences. I'm having a hard time f...
1 comments posted 18yrs
posted by mloulah
1 comments posted 18yrs posted by mloulah

ethernet phy or mac

Hi Does anyone have any experiences with connecting a MAC rather than a PHY to a spartan(3e). I don't know yet whether...
4 comments posted 18yrs
posted by colin_toogood
4 comments posted 18yrs posted by colin_toogood

FPGA to FPGA Bus

Hi I would like to connect 3 FPGA devices together using a 32-bit bus. Also would like all 3 to be masters on the bus....
5 comments posted 18yrs
posted by maxascent
5 comments posted 18yrs posted by maxascent

RTM ERROR:fail to get the remote thread list.

when Debug in NIOS II,,the waring message is :RTM ERROR:fail to get the remote thread list.. why?
0 comments posted 18yrs
posted by cppcpldfpga
0 comments posted 18yrs posted by cppcpldfpga

Xilinx:is it possible to install Impact 9.1only?

Hi,in a previous post i asked about an easy way to have my fpga self programmed at power on Xapp 974 shows how to progr...
3 comments posted 18yrs
posted by bliscachiocciolinatiscali.it
3 comments posted 18yrs posted by bliscachiocciolinatiscali.it

Xilinx FIFO Flag Question

I generated a 32-bit by 1024 entry FIFO using the FIFO Generator. The FIFO is an independently-clocked BRAM that has a...
0 comments posted 18yrs
posted by mottoblatto
0 comments posted 18yrs posted by mottoblatto

Xilinx timing constraints incorrect?

Hello all, I am working on a design for a Xilinx V2P50 and I am trying to diagnose possible timing issues because the h...
12 comments posted 18yrs
posted by paragon.john
12 comments posted 18yrs posted by paragon.john

profiling in modelsim

Hi, Iam working on profiling , using 6.1d version, memory profiling reports generated for my project code is interims o...
1 comments posted 18yrs
posted by vishii4u
1 comments posted 18yrs posted by vishii4u

FIFO depth

I have doubt in calculating FIFO depth. Transmitter is writing 16 bit data with a frequency of 40 KHz. Receiver is read...
4 comments posted 18yrs
posted by vishnuprasanth
4 comments posted 18yrs posted by vishnuprasanth

Altera devices connecting to DDR memory.

Hi In Cyclone II ep2c5 pinouts document: http://www.altera.com/literature/dp/cyclone2/ep2c5.pdf Some pins have addition...
5 comments posted 18yrs
posted by "SwietyMikolaj["
5 comments posted 18yrs posted by "SwietyMikolaj["