Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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FIFO depth
I have doubt in calculating FIFO depth. Transmitter is writing 16 bit data with a frequency of 40 KHz. Receiver is reading 8 bit data with a frequency of 60 KHz. What is the depth of FIFO I need to...
4
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16 years ago
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Altera devices connecting to DDR memory.
Hi In Cyclone II ep2c5 pinouts document: pins have additional discription: DQxxx DQSxx DMxx. DQS signals are assign to this pins because this pins are routed directly to the clock control block and...
5
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16 years ago
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5 | |
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where to download latest systemc libararies?
where to download latest systemc libraries? i checked but there is no link for download.
1
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16 years ago
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1 | |
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MIG for Linux?
So I thought I would try out this MIG thing I see mentioned occasionally, But according to Software Requirements - ISE 9.2.01i - Windows XP (32 bit) So is MIG really windows only? I currently have ISE...
7
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16 years ago
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7 | |
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Newbie,the simplest way to program an FPGA at home?
Hi i 'm trying to practice VHDL at home,until today i did some things using obsolete Lattice and Xilinx CPLD. One year ago i bought a Spartan educational board from Digilent with a programming cable...
7
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16 years ago
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7 | |
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Quartus II Web Edition License - SOPC Builder generation?
If I have the web edition license, is it still possible to use the SOPC builder? I'm just trying to build one of the projects in the tutorial... Thanks, Eric ------------------------ This is the error...
7
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16 years ago
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7 | |
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Cyclone II on Altera DE2 Board - DRAM Timing on 18 inches?
I've been scouring the newsgroups for DRAM discussions and I ran into several that discussed the timing even over "short" distances. I'm trying to design a DRAM controller to write/read a pattern to...
1
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16 years ago
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NgdBuild:455 Multiple Drivers
I'm working with XILINX ise 9.2i; designing a deserializer & using 2 DCM's in sequence to generate 4 100MHz clocks (each 90 degrees out of phase) from the 50MHz local clock on a Spartan-3 FPGA The...
1
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16 years ago
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1 | |
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Graphical VHDL Viewer ?
Hi all, Does anyone know a free/simple software that would use vhdl files to produce a graphical view ? The goal is to have a easier and faster read of the architecture of a vhdl file and its...
9
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16 years ago
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9 | |
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Xilinx OCM memory use limitations ?
Hi all, We are building a very simple SOC ( PPC 405, internal memory, UART light) in a V4FX60, with a very simple firmware. The point is that when we use the PLB_BRAM memory, the GDB debugger works...
2
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16 years ago
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2 | |
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Quartus II 7.2 web edition - Linux or not?
I just got an email from Altera, saying: ear Altera Customer, The new Quartus® II Web Edition Software version 7.2 is now available for download. New features include: [...blah...] * Get complete OS...
12
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16 years ago
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Re: UK Supplier XILINX spartan 3 development board??
Hi Mike, True enough! My serious point, although hidden by the sarcasm, is it's often worth shelling out up front to get what you really want, rather than saving a few quid on something that might end...
2
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16 years ago
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Xiinx ERROR:PhysDesignRules:10
Hi all, I've got a design that can be built in 2 different configurations, controlled via a VHDL constant / if-generate in a sub-module. Each configuration uses a particular set of I/O pins and leaves...
1
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16 years ago
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FPGA tools under VMware or Parallels on a Mac?
Which vendor's FPGA development and USB download tools have people found to work reliably on a Mac or MacBook under either the Parallels or VMware virtualizers, running Windows XP, 2k or linux? If so,...
5
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16 years ago
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Cyclone II SSTL-2 on-chip resistors
Hi, I'm trying to build a board that will use a DDRAM PC2700 memory module connected to a Cyclone II FPGA. It uses SSTL-2 signaling, and one thing I really don't understand is why the on-chip series...
2
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16 years ago
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2 |