Latest threads in Field-Programmable Gate Arrays

FPGA evaluation board with > 32K slices

Hi We are looking for an FPGA evaluation board to get a simple RISC processor running. It should have at least 32K slic...

3 18yrs

Philipp

3 18yrs Philipp

setup ETHERNET UDP link suing spartan-3E starter kit

hi, i need to 100BASET connection with a PC using xilinx spatan-3E board and lan83c185 chip.i need a bare system just t...

1 18yrs

dilan2005

1 18yrs dilan2005

Is it possible to define an Integer so it could be incremented and return to 0.

First of all, sorry for my English. What I want is: variable int : integer range 0 to 64:=0; begin process begin int :=...

21 18yrs

pbantunez

21 18yrs pbantunez

VirtexE LVDS driver

Hi to all, I am confused about one thing that if I want to use LVDS in VirtexE, should I feed the Vcco of the desired b...

1 18yrs

eneserdin

1 18yrs eneserdin

Feedback on Stratix III

Hi everybody, As Altera claims that Stratix III engineering samples are available today for some customers who subcribe...

0 18yrs

supalexh

0 18yrs supalexh

Power up Behavior of Virtex5 IOs

Hi, I have a design which has Virtex5 LX30T. On a particular IO, I have a external pull up of 4.7K, which connects to a...

2 18yrs

togoli

2 18yrs togoli

How to view resource utilization by hierarchy?

Hello, I am interested in looking at the breakdown of resource utilization for a design I have done in a Virtex-II Pro...

0 18yrs

paragon.john

0 18yrs paragon.john

Place-and-Route : Intel vs AMD

Anybody heard of a recent benchmark comparing both Intel and AMD high- end processors regarding their Place-and-Route (...

9 18yrs

louis.dupont

9 18yrs louis.dupont

Connecting different FPGAs using LVDS

Hi, I am trying to connect a Virtex4 and a VirtexE FPGA by LVDS signals. When I look through oscilloscope I see a good...

5 18yrs

eneserdin

5 18yrs eneserdin

Cant capture data with Chipscope 7.1

Hi I have a simple VHDL counter modul that I wanna debug with Chipscope 7.1 on a Virtex II board: library IEEE; use IEE...

6 18yrs

Paul

6 18yrs Paul

Purchasing IC components at a good price

If you are looking to buy components I have a friend works in class-ic and she will give you a good price

2 18yrs

thuyp

2 18yrs thuyp

XAPP924 Doesnt work

Hi All , I new to FPGA development tools from xilinx. I am following an application note number XAPP924 to use EPC modu...

2 18yrs

niladri1979

2 18yrs niladri1979

Multiple UCF support in Xilinx ISE

Hi, I need to know is it possible to add multiple ucf files in an ISE project? I tried to do this by splitting the orig...

8 18yrs

sheikh.m.farhan

8 18yrs sheikh.m.farhan

How to program and initialize Lattice XP devices

I am planning to use the Lattice XP flash based FPGA in a new design and I have not worked with it before. It seems to...

4 18yrs

gnuarm

4 18yrs gnuarm

Xilinx ISE 7.1 to 9.2 Width Mismatch

I am getting 'width mismatch' warning on the char_slv assignement and text garbage after synthesis on this code that ra...

1 18yrs

bradsmallridge

1 18yrs bradsmallridge

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