Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Synthesizing big RAMs
Hi, I would like to implement a 64K x 16-bit RAM, but no FPGA of my design tool (Xilinx ISE) has enough blocks or LUTs. Is it possible to implement such big RAMs in FPGAs? My code is VHDL. Thanks
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16 years ago
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Creation of BUGMUX from non clock signals
Hi, I have a piece of VHDL code that is causing Xilinx ISE to pass non clock lines through BUFGMUXes instead of using BUFGMUXes with only clock lines. I currently cannot put the code on here since...
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16 years ago
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How to program FPGA permanently?
Hello, I have downloaded my program to FPGA and it works as it supposed to do. However, I need to download it every time after I switch power off. Hence I wonder - how to save program on FPGA...
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16 years ago
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Identification of FPGA Development Board
Hi together, recently, I acquired an old FPGA development board out of the remainder of stock of a company. The board has quite powerful FPGAs on it, however, I can't find any information about it. It...
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16 years ago
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MPMC3, DDR 32Mx16, S3E1200, single bank, impossible?
Hi all, I wonder if it possible to make a MIG1.73 compliant design by connecting 32Mx16 DDR SDRAM to a single bank on a FG320 Spartan3E1200? Btw MIG1.73 compliance is a must for using the MPMC3 memory...
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16 years ago
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Spartan3 vs cyclone
Hi, I've a basic question about spartan3. I'm used to work with altera's FPGA with size unit in logic cells. I've to use a spartan 3 FPGA, and its size is in gates. My question : how can I compare the...
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16 years ago
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Using DDR SDRAM as single data rate ..?
Is it possible to use DDR SDRAM as single data rate SDRAM and thus eliminate the need for DCM's and tight clock frequency specifications ..? The idea is to ignore the data sent on the second flank,...
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16 years ago
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V5 System Monitor
Hi Guys, Has anybody used a V5 Sys Monitor.. I need some insight on the Aux IOs The UG 192 (refer pg 39) says that once you instantiate the Sys Mon, you can use any number of Aux IOs as analog and the...
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16 years ago
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Warning 'clock has been changed'
Hello All, I have got a warning (below) during implementation of my design which uses 50 MHz clock on Spartan 3E 1600E Microblaze Development Kit. What could be a reason for this warning and how it...
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16 years ago
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Please, help - I have got confused about package type
Hello, I have Spartan 3E1600E Microblaze Development kit with FPGA marked as: ----------------------------- Xilinx SPARTAN XC3S1600E FGG320DGQO617 A1408025A1 4C ----------------------------- KOREA How...
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16 years ago
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True Dual Port RAM
I am unable to infer a True Dual Port RAM in ispLEVER using VHDL. I'm targetting the Lattice ECP2M using Synplify. Even the provided example located in isptools7_0examples...
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16 years ago
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Low Power CPU Implementation
Hi all. I am doing a small Processor implementation (with the performance somewhat like an 8051 CPU), and I am designing for "as low power as possible". I want to use reconfigurable logic as I am...
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16 years ago
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Real examples of metastability causing bugs
Hello, Suppose that I'm sampling an asynchronous signal with a FF, without using any synchronizers before it. This FF will become metastable from time to time with a MTBF depending on the device's...
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16 years ago
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passive serial quaestion
Hi, Everyone, I have one question regarding passive serial programing of altera fpga. Can flex 8000 series be programed in the same way as cyclone families. Which programing file is used when fpga is...
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16 years ago
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Bad micro blaze behaviour during power off
setup: On one of our designs we are using a Xilinx partan3 FPGA (XC3S500E -4 FT(G)256 stepping1) and an spi flash (M25P40-VMN6) to store FPGA code, callibration data, board settings,... Problem...
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16 years ago
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