Field-Programmable Gate Arrays

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VirtexE LVDS driver

Hi to all, I am confused about one thing that if I want to use LVDS in VirtexE, should I feed the Vcco of the desired b...
1 comments posted 18yrs
posted by eneserdin
1 comments posted 18yrs posted by eneserdin

Feedback on Stratix III

Hi everybody, As Altera claims that Stratix III engineering samples are available today for some customers who subcribe...
0 comments posted 18yrs
posted by supalexh
0 comments posted 18yrs posted by supalexh

Power up Behavior of Virtex5 IOs

Hi, I have a design which has Virtex5 LX30T. On a particular IO, I have a external pull up of 4.7K, which connects to a...
2 comments posted 18yrs
posted by togoli
2 comments posted 18yrs posted by togoli

How to view resource utilization by hierarchy?

Hello, I am interested in looking at the breakdown of resource utilization for a design I have done in a Virtex-II Pro...
0 comments posted 18yrs
posted by paragon.john
0 comments posted 18yrs posted by paragon.john

Place-and-Route : Intel vs AMD

Anybody heard of a recent benchmark comparing both Intel and AMD high- end processors regarding their Place-and-Route (...
9 comments posted 18yrs
posted by louis.dupont
9 comments posted 18yrs posted by louis.dupont

Connecting different FPGAs using LVDS

Hi, I am trying to connect a Virtex4 and a VirtexE FPGA by LVDS signals. When I look through oscilloscope I see a good...
5 comments posted 18yrs
posted by eneserdin
5 comments posted 18yrs posted by eneserdin

Cant capture data with Chipscope 7.1

Hi I have a simple VHDL counter modul that I wanna debug with Chipscope 7.1 on a Virtex II board: library IEEE; use IEE...
6 comments posted 18yrs
posted by Paul
6 comments posted 18yrs posted by Paul

Purchasing IC components at a good price

If you are looking to buy components I have a friend works in class-ic and she will give you a good price
2 comments posted 18yrs
posted by thuyp
2 comments posted 18yrs posted by thuyp

XAPP924 Doesnt work

Hi All , I new to FPGA development tools from xilinx. I am following an application note number XAPP924 to use EPC modu...
2 comments posted 18yrs
posted by niladri1979
2 comments posted 18yrs posted by niladri1979

Multiple UCF support in Xilinx ISE

Hi, I need to know is it possible to add multiple ucf files in an ISE project? I tried to do this by splitting the orig...
8 comments posted 18yrs
posted by sheikh.m.farhan
8 comments posted 18yrs posted by sheikh.m.farhan

How to program and initialize Lattice XP devices

I am planning to use the Lattice XP flash based FPGA in a new design and I have not worked with it before. It seems to...
4 comments posted 18yrs
posted by gnuarm
4 comments posted 18yrs posted by gnuarm

Xilinx ISE 7.1 to 9.2 Width Mismatch

I am getting 'width mismatch' warning on the char_slv assignement and text garbage after synthesis on this code that ra...
1 comments posted 18yrs
posted by bradsmallridge
1 comments posted 18yrs posted by bradsmallridge

Synthesizing big RAMs

Hi, I would like to implement a 64K x 16-bit RAM, but no FPGA of my design tool (Xilinx ISE) has enough blocks or LUTs....
7 comments posted 18yrs
posted by x
7 comments posted 18yrs posted by x

Creation of BUGMUX from non clock signals

Hi, I have a piece of VHDL code that is causing Xilinx ISE to pass non clock lines through BUFGMUXes instead of using B...
2 comments posted 18yrs
posted by axr0284
2 comments posted 18yrs posted by axr0284