Using DDR SDRAM as single data rate ..?

You still have to feed the DDR with appropriate clock signals, because it'll always work with differential clock. If you're working with the Spartan 3E starter kit this means that the clock frequency should be in the range of

75-133 MHz, the DCM is handy because it easily synthesizes these frequencies starting from the 50 MHz soldered clock.

I'm not sure, but I think that once yuo've done the setup (initialization) correctly, it doesn't make any sense to ignore the second data trunk because it should come at (almost) no additional expense.

Andrew

But does the clock frequency have to be within 75-133 MHz range when the data provided by the DLL on the second flank is ignored?, plain SDRAM can be clocked down to a few kHz according to Micron (a dram manufacturer). It would at least save some DCMs and pcb layout headache.

All DDR memories spec a minimum clock frequency. Whether this is due to the internal DLL or other dynamic structures may be vendor dependent. Usually they have the ability to turn off the DLL using a mode register bit, but you'll be doing a lot of experimenting to see if that works. Also note that while you can send the same data twice to emulate single data rate, you still need to meet more stringent timing if you want the chip to see the same write data on both clock edges. If you only meet timing for the second edge, then you'll have to live with tighter timing when you read, because the RAM will send data that changes mid-cycle.

You also can't just use some existing SDR IP, since at least the start-up and mode register settings are different, and you'll need to drive the DQS pins on writes, even if you don't use them for reads.

I'm assuming you have a board that already has DDR memory on it and you just want to use it more easily? If you're designing a new board you should really look into using the SDR chips instead.

I've always wondered that myself. I hope someone who knows will understand and answer your question. So far people seem to be stuck on the clock rate issue instead of the question of whether you can just store/read the same data on the rising/falling edge during the transfers and treat it like an SDR SDRAM.

--
Ben Jackson AD7GD

http://www.ben.com/

In my opinion it should possible, but if you are a beginner. Do not start learning with a design of a memory controller. You will not successful and very frustrated. :-(

At DDR-Memories the timing critical operation is read. You must delay the DQS-Signal or a phase synchron clock signal by 90°. With this clock signal the data from the memory is sampled in two flip-flops one at rising a second at falling edge.

Assuming you double your data at write. This halves the memory size by two.

When you read back your data, you can shift the DQS direct by 180°(done with a simple inverter) and sample between the data0 and data1. The timing window should also doubled.

But this is only possible, if the read data is stable from setup of data0 to the end of data1. I think this will not guaranteed by any memory manufacturer.

Remark: This is only a theoretical assumption!

Daniel

snipped-for-privacy@yahoo.com schrieb:

There may be a "chicken & egg" problem doing this.

Some DDR's have a "x.5 clock" latency - you need to get data on the "other" edge.

To re-configure the part, you (most likely) need to send a configuration command which will use both edges.

Try it and see! The Micron models should simulate this properly.

G.

Ah yes, I hadn't considered the mode registers.

--
Ben Jackson AD7GD

http://www.ben.com/

While the mode registers are different, no command requires both edges. "Commands" are all captured on the rising edge of the clock and use only the control and address lines. Only the data is double-rate.

My main reason for using single-data-rate parts is the simplicity of the wiring for the LVCMOS signals vs. SSTL. In small designs (1 32-bit SDR vs. 1 16-bit DDR) the pin savings for data can be lost in the additional Vref and control pins, especially on Xilinx parts that require all Vref pins in a bank to be tied together.

I imagine if you started with a controller intended for DDR memory and only treat the data as SDR, you could get it to work. But as I mentioned before, your write data needs to set up to both edges of the clock in order for the read data to have extended setup time. If you slow the clock sufficiently, you may as well run the data DDR anyway. And you still need to generate DQS on a quadrature clock. So you would only save a DLL or DCM if you generated the clocks by dividing down some higher frequency.

By the way, did you look into mobile DDR parts? I believe these are intended to run at low frequencies in order to save power and don't require SSTL interfacing.

Regards, Gabor