Hi, I have a piece of VHDL code that is causing Xilinx ISE to pass non clock lines through BUFGMUXes instead of using BUFGMUXes with only clock lines. I currently cannot put the code on here since it's proprietary. I just wanted to know if anybody had any general idea of what could be causing it. Amish
If you have a very high fanout on one line, sometimes a synthesizer will instantiate a global clock buffer for that line. But it's also possible that the line is, unbeknownst to you, a clock. You might have accidentally inferred a gated clock or a latch so that the line is actually driving a clock input somewhere. -Kevin
There was a recent thread discussing trying to use the clock lines for a reset signal:
or:
In it, Austin stated that prior to the Virtex 5 it was not possible to route a logic signal on a clock line.
What chip are you using?
If it is prior to the Virtex 5, your logic is creating a register or a latch using that signal. If you look in the place and route report, it has a list of clocks and their fan outs. See if it list your signal as a clock. You could also load the design in the FPGA editor and select that signal to see where it goes.
Regards,
John McCaskill
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