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Low Power CPU Implementation

Hi all. I am doing a small Processor implementation (with the performance somewhat like an 8051 CPU), and I am designing for "as low power as possible". I want to use reconfigurable logic as I am interested in the the flexibility and the possibility of adding additional logic to my design.

Already with aid of the helpful users of this NG I am looking at three competing products. The Coolrunner II CPLD from Xilinx The MAXII from Altera The IGLOO FPGA from Actel

When looking at the specs, IGLOO seems to provide the best scores, however, these come from the manufacturer themselves, so I wondered if somebody has worked with low power designs with the above mentioned devices - and could give me some "real-life" experiences?

If Actels figures are correct, I must admit I have never worked with their development tools. How are these in user-friendlyness and quality in comparison with for example the Xilinx product (ISE and EDK). Any experiences?

I am looking very much forward to her from you The Best of Regards :-)

Reply to
Rgr
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I can't speak for Libero but Actel Designer (P&R only) is logical and very easy to use. The only downside is that P&R takes ages which might be due to their fine grain architecture.

If you are planning to use an Igloo then I would suggest to get their AGL600 prototype board and not the Icicle since the AGL125 might be too small for your processor design. I have just done a quick test with the Oregano 8051 and it takes 5178 Tiles (AGL125 only has 3072)

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Hans

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Reply to
HT-Lab

If he goes for an Igloo AGL600 then he can use 14Kbyte of internal memory. For "young" engineers :-) that might sound like absolute peanuts, but if you grew up in the ZX81/Acorn Atom/Vic20/Junior/.. era then this is plenty of memory. I just ported one of my designs to a Spartan-3E S500 and could create a 40Kbyte internal memory using just the blockrams, this is plenty of memory for a small embedded control system.

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Hans

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Reply to
HT-Lab

"as low power as possible" and PLD are somewhat mutually exclusive.

Real designs need some form of timebase, and FPGAs have no low power OSC solutions, so you will need two chips. The better microcontrollers (SiLabs have good 80C51 examples) have sub uA RTC modes, and low uA on chip Osc, and also very fast wakeup of their fast CAL osc's.

32KHz crystals can give very low uA, precison timebase solutions, if you can tolerate their size/startup times/cost/shock trade offs. RC Osc's represent a compromise in uA and precison : choose one, not both :) CAL-OSC offerings are improving all the time.

Then you likely also need Brown out detection

So you will be best sweeping all the low power timing/analog stuff you can into a STD uC device, and then doing what is left over in a FPGA/ CPLD. For very lowest power, you may want to remove the FPGA core Vcc, and run just the uC.

The Lattice MACH4000Z, and Atmel ATF1502BE series are low uA CPLD offerings, for moderate amounts of Logic.

Altera have just released their MAX IIZ, so for more logic that's another candidate.

-jg

Reply to
-jg

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