setup: On one of our designs we are using a Xilinx partan3 FPGA (XC3S500E -4 FT(G)256 stepping1) and an spi flash (M25P40-VMN6) to store FPGA code, callibration data, board settings,...
Problem description: Random SPI commands on the SPI bus from the FPGA to the flash are logged during a power down of the board. Sometimes a complete SPI write sequense is logged which makes the flash content corrupt.
root cause: Power down of the FPGA is not correct accoarding to the spec. The fall time of the power supply is to long. this results in a bad behaviour of the micro Blaze(uB). During power down the pointer of the uB is jumping to a random place in the uB code. From this point the uB executes several actions depending on the fall time of the power supply. It happens that the pointer jumps to the "write_spi_flash" function in the code.
solution: The best solution is to make the power off sequense of the FPGA according to the spec. It is possible to place a power monitor on the board but this results in a redesign of the board and we do not prefere to do so.
question: Is there somebody who knows another solution that does not require a redesign of the board?