Latest threads in Field-Programmable Gate Arrays

Synthesizing big RAMs

Hi, I would like to implement a 64K x 16-bit RAM, but no FPGA of my design tool (Xilinx ISE) has enough blocks or LUTs....

7 18yrs

x

7 18yrs x

Creation of BUGMUX from non clock signals

Hi, I have a piece of VHDL code that is causing Xilinx ISE to pass non clock lines through BUFGMUXes instead of using B...

2 18yrs

axr0284

2 18yrs axr0284

How to program FPGA permanently?

Hello, I have downloaded my program to FPGA and it works as it supposed to do. However, I need to download it every tim...

4 18yrs

vladimir.v.korostelev

4 18yrs vladimir.v.korostelev

Identification of FPGA Development Board

Hi together, recently, I acquired an old FPGA development board out of the remainder of stock of a company. The board h...

4 18yrs

koltes

4 18yrs koltes

MPMC3, DDR 32Mx16, S3E1200, single bank, impossible?

Hi all, I wonder if it possible to make a MIG1.73 compliant design by connecting 32Mx16 DDR SDRAM to a single bank on a...

4 18yrs

ales.gorkic

4 18yrs ales.gorkic

Spartan3 vs cyclone

Hi, I've a basic question about spartan3. I'm used to work with altera's FPGA with size unit in logic cells. I've to us...

6 18yrs

michel.talon

6 18yrs michel.talon

Using DDR SDRAM as single data rate ..?

Is it possible to use DDR SDRAM as single data rate SDRAM and thus eliminate the need for DCM's and tight clock frequen...

8 18yrs

posedge52

8 18yrs posedge52

V5 System Monitor

Hi Guys, Has anybody used a V5 Sys Monitor.. I need some insight on the Aux IOs The UG 192 (refer pg 39) says that once...

0 18yrs

mailtoakshat

0 18yrs mailtoakshat

Warning 'clock has been changed'

Hello All, I have got a warning (below) during implementation of my design which uses 50 MHz clock on Spartan 3E 1600E...

3 18yrs

vladimir.v.korostelev

3 18yrs vladimir.v.korostelev

Please, help - I have got confused about package type

Hello, I have Spartan 3E1600E Microblaze Development kit with FPGA marked as: ----------------------------- Xilinx SPAR...

3 18yrs

vladimir.v.korostelev

3 18yrs vladimir.v.korostelev

True Dual Port RAM

I am unable to infer a True Dual Port RAM in ispLEVER using VHDL. I'm targetting the Lattice ECP2M using Synplify. Even...

4 18yrs

Colin.Hankins

4 18yrs Colin.Hankins

Low Power CPU Implementation

Hi all. I am doing a small Processor implementation (with the performance somewhat like an 8051 CPU), and I am designin...

3 18yrs

rgrworking

3 18yrs rgrworking

Real examples of metastability causing bugs

Hello, Suppose that I'm sampling an asynchronous signal with a FF, without using any synchronizers before it. This FF w...

66 18yrs

eliben

66 18yrs eliben

passive serial quaestion

Hi, Everyone, I have one question regarding passive serial programing of altera fpga. Can flex 8000 series be programed...

4 18yrs

Zorjak

4 18yrs Zorjak

Bad micro blaze behaviour during power off

setup: On one of our designs we are using a Xilinx partan3 FPGA (XC3S500E -4 FT(G)256 stepping1) and an spi flash (M25P...

10 18yrs

jeroen.claes

10 18yrs jeroen.claes

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