Field-Programmable Gate Arrays

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How to program FPGA permanently?

Hello, I have downloaded my program to FPGA and it works as it supposed to do. However, I need to download it every tim...
4 comments posted 18yrs
posted by vladimir.v.korostelev
4 comments posted 18yrs posted by vladimir.v.korostelev

Identification of FPGA Development Board

Hi together, recently, I acquired an old FPGA development board out of the remainder of stock of a company. The board h...
4 comments posted 18yrs
posted by koltes
4 comments posted 18yrs posted by koltes

Spartan3 vs cyclone

Hi, I've a basic question about spartan3. I'm used to work with altera's FPGA with size unit in logic cells. I've to us...
6 comments posted 18yrs
posted by michel.talon
6 comments posted 18yrs posted by michel.talon

Using DDR SDRAM as single data rate ..?

Is it possible to use DDR SDRAM as single data rate SDRAM and thus eliminate the need for DCM's and tight clock frequen...
8 comments posted 18yrs
posted by posedge52
8 comments posted 18yrs posted by posedge52

V5 System Monitor

Hi Guys, Has anybody used a V5 Sys Monitor.. I need some insight on the Aux IOs The UG 192 (refer pg 39) says that once...
0 comments posted 18yrs
posted by mailtoakshat
0 comments posted 18yrs posted by mailtoakshat

Warning 'clock has been changed'

Hello All, I have got a warning (below) during implementation of my design which uses 50 MHz clock on Spartan 3E 1600E...
3 comments posted 18yrs
posted by vladimir.v.korostelev
3 comments posted 18yrs posted by vladimir.v.korostelev

Please, help - I have got confused about package type

Hello, I have Spartan 3E1600E Microblaze Development kit with FPGA marked as: ----------------------------- Xilinx SPAR...
3 comments posted 18yrs
posted by vladimir.v.korostelev
3 comments posted 18yrs posted by vladimir.v.korostelev

True Dual Port RAM

I am unable to infer a True Dual Port RAM in ispLEVER using VHDL. I'm targetting the Lattice ECP2M using Synplify. Even...
4 comments posted 18yrs
posted by Colin.Hankins
4 comments posted 18yrs posted by Colin.Hankins

Low Power CPU Implementation

Hi all. I am doing a small Processor implementation (with the performance somewhat like an 8051 CPU), and I am designin...
3 comments posted 18yrs
posted by rgrworking
3 comments posted 18yrs posted by rgrworking

Real examples of metastability causing bugs

Hello, Suppose that I'm sampling an asynchronous signal with a FF, without using any synchronizers before it. This FF w...
66 comments posted 18yrs
posted by eliben
66 comments posted 18yrs posted by eliben

passive serial quaestion

Hi, Everyone, I have one question regarding passive serial programing of altera fpga. Can flex 8000 series be programed...
4 comments posted 18yrs
posted by Zorjak
4 comments posted 18yrs posted by Zorjak

Bad micro blaze behaviour during power off

setup: On one of our designs we are using a Xilinx partan3 FPGA (XC3S500E -4 FT(G)256 stepping1) and an spi flash (M25P...
10 comments posted 18yrs
posted by jeroen.claes
10 comments posted 18yrs posted by jeroen.claes

Processor in CPLD

Hi. I would like to hear your opinion on the possibility of implementing a processor in a CPLD? The functionality does...
11 comments posted 18yrs
posted by rgrworking
11 comments posted 18yrs posted by rgrworking

Viterbi Decoder

Hi, I am designing a viterbi decoder with r=1/2 and k=7 on fpga but don't want to design from scratch. Can one share so...
0 comments posted 18yrs
posted by sarah.stregel
0 comments posted 18yrs posted by sarah.stregel