Spartan3 vs cyclone

Take a number of designs, synthesize using both XST and QNS (or Precision/Synplify if you have an all vendor version) and compare.

Hans

Thank you for your answer, but I've synplify only for Xilinx FPGA..

regards, Michel

Michel

Worth trying a comparison using ISE Webpack for Xilinx and Quartus Webpack for the Altera. The LUT structures on the Altera are not massively different to Xilinx with the exception the Altera often uses one of the LUT inputs to feed the flip-flop input and Xilinx does not. That sometimes gives a small advantage to Xilinx. The other thing Xilinx have that might be better for some designs is the use of LUTs for local SRAM and possibly more useful the SRL16 mode of the LUT. The latter mode can save lots of logic versus an Altera solution in some designs where it is useful. Other things to consider are how well the number and size of blockrams fit your application. Same goes for the DSP features.

On pricing which of the 2 vendors is best is very much design dependent, volume dependent, and often just how much a given vendor wants the business at that moment in time. Sectors and customers go in and out of favour so in 2 different weeks you might get different answers.

John Adair Enterpo> >

You're used to working with Altera's Logic Elements (LEs) and you don't know how to compare this with the Spartan3 because these chips are specified by gate count?

Look at the darned data sheet! I've a feeling you'l find the data you need in the first pages. The "system gates" column is followed "Equivalent Logic Cells." As a seasoned Xilinx data sheet reader myself, I've learned to ignore this column and look at "Slices" and multiply by 2 instead since the "equivalent" means multiplying by a rude, evasive, misleading marketing factor.

Thanks for your answers, I wasn't sure that Xilinx logic cells and altera logic elements were equivalent, but it seems to be.. So thank you.

Best regards, Michel.

They are equivalent. Mostly... The LUTs in a Xilinx device can be used as a 16x1 bit memory or a variable length (up to 16 bit) shift register. This gives you a total of 18 flipflops per slice in a Xilinx device versus 2 in an Altera device.

Using the LUTs as memory is a very efficient way to create small memories. Because such a memory is built from multiple elements which can be place freely, it is likely the routing is less constrained than in an Altera device.

Using the LUTs as a shift register allows to create very efficient clock dividers and FIFO's.

An efficient way of using LUT rams can be in designs in which multiple channels are processed in sequence. By using LUT memory as registers instead of flipflops to keep intermediate results the savings can be enourmous. Almost the same amount of logic for 1 channel can deal with up 16 channels.