Field-Programmable Gate Arrays

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fpga pin to pin conecting

Hi everyone Can someone please help me. If I have to connect two FPGA circuits on the same board and their pins are not...
5 comments posted 18yrs
posted by Zorjak
5 comments posted 18yrs posted by Zorjak

sine and cosine wave generation

Can anyone give guidelines on how to generate sine and cosine wave in VHDL?
9 comments posted 18yrs
posted by FPGA.unknown
9 comments posted 18yrs posted by FPGA.unknown

Debbuging a RISC processor on an FPGA

Hi I have implemented a RISC architecure and RTL simulation in Modelsim works fine. So the next step would be to run th...
13 comments posted 18yrs
posted by pg4100
13 comments posted 18yrs posted by pg4100

Where has Xilnet gone?

Hi all , I am new to xilinx tool and currently I am working with a project constructed using EDK 7.1. I am using EDK 9....
5 comments posted 18yrs
posted by niladri1979
5 comments posted 18yrs posted by niladri1979

Read/Write SRAM on Spartan3 Starter kit

Hi all, I am sorry if this problem has been answered but I cannot find much help from the archive. I am trying to test...
3 comments posted 18yrs
posted by tklau
3 comments posted 18yrs posted by tklau

libusb-driver and Spartan3-AN Eval kit woes

Hi ! I appologize if that has been dealt with already, though I haven't found an answer in the archives. I have an x86_...
0 comments posted 18yrs
posted by ben.herrenschmidt
0 comments posted 18yrs posted by ben.herrenschmidt

Virtex4 burn-in failure

Hello, I've observed a failure of one of our Virtex4-based products that is a bit puzzling. The device had been in oper...
10 comments posted 18yrs
posted by msn444
10 comments posted 18yrs posted by msn444

Final call for papers

Final call for papers The 2008 MULTICONF (website: www.PromoteResearch.org ) will be held during July 7-10 2008 in Orla...
0 comments posted 18yrs
posted by jeedward
0 comments posted 18yrs posted by jeedward

BRAM Readback

Hi all, Is there a simple way to read back data from Virtex5 BRAMs preferable over JTAG by XSFV/SVF commands? Best regar...
2 comments posted 18yrs
posted by biker
2 comments posted 18yrs posted by biker

Spartan 3AN LVDS I/O

I have a working Spartan 3E design that I am porting to XC3S200AN. It has a handful of instantiated ODDR2s connected to...
4 comments posted 18yrs
posted by google
4 comments posted 18yrs posted by google

opb_emc_v1_10_b

Hi all , Is there any place where I can download opb emc 1.10.b as my lates EDK istallation doesnt have it? BR Rate
4 comments posted 18yrs
posted by niladri1979
4 comments posted 18yrs posted by niladri1979

Timing constraints not applied, ISE & SynplifyPro

Hi, I'm a new synplify pro user. This tool seems to be much powerfull than XST for apply timing constraints. But there...
2 comments posted 18yrs
posted by michel.talon
2 comments posted 18yrs posted by michel.talon

Resource utilization broken down by hierarchy?

Hello, I am interested in looking at the resource utilization of a design I am working on broken down based on the RTL...
4 comments posted 18yrs
posted by paragon.john
4 comments posted 18yrs posted by paragon.john

FPGA evaluation board with > 32K slices

Hi We are looking for an FPGA evaluation board to get a simple RISC processor running. It should have at least 32K slic...
3 comments posted 18yrs
posted by Philipp
3 comments posted 18yrs posted by Philipp