Latest threads in Field-Programmable Gate Arrays

how we can prove that really the AES 256 is used to crypt the Bitstream in virtex 5

As my current project is about the security that Xilinx embeds in the Virtex 5 , i have some points that i couldn't und...

0 18yrs

swissiyoussef

0 18yrs swissiyoussef

Very simple VHDL problem

Hi there - I am slowly teaching myself VHDL this weekend. I am getting an error that I do not understand: "parse error,...

17 18yrs

nleahcim

17 18yrs nleahcim

Synthesis Comparison

Hello, I am writing my report on a university project. The project work involved an FPGA implementation of a neural net...

4 18yrs

obviouslyadummy

4 18yrs obviouslyadummy

How to instantiate macro in verilog

Dear all, I've designed a macro, and put "rring r1(.en(en),.ro(ro)); ... to instantiate ring macro, but failed. Any one...

5 18yrs

hlyu

5 18yrs hlyu

Xilinx DDR2 Interface

I used the latest version of MIG to generate pinouts for a Virtex 4 DDR2 interface. In addition to all the usual Addres...

6 18yrs

ben

6 18yrs ben

Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff

Hello, I am new to this FPGA stuff and I wanted to purchase a starter kit and get volume pricing for a few Xilinx FPGA'...

4 18yrs

or09uus

4 18yrs or09uus

Chipscope is Failing

It works fine for Webpack 10.1 but does not work for Chipscope. I get the following error on chipscope: COMMAND: open_p...

0 18yrs

oshea

0 18yrs oshea

New to FPGA : Timing Closure

Hi All, I am new to FPGA development , I have encountered a timing closure problem and would appreciate some advice fro...

2 18yrs

niladri1979

2 18yrs niladri1979

Re: Chip photos of old FPGAs

> I recently found a couple of XC2018 in a drawer. Although > these will probably never see any use again it got me > t...

0 18yrs

ehliar-nospam

0 18yrs ehliar-nospam

XST design frequency setting

Hey everybody, Just started using Xilinx XST as my synthesis tool and I'm just looking for the command line instruction...

3 18yrs

robquigley

3 18yrs robquigley

Survey: FPGA PCB layout

Does anybody out there have a good methodology for determining your optimal FPGA pinouts, for making PCB layouts nice,...

93 18yrs

dhschetz

93 18yrs dhschetz

attached a 2nd peripheral to FSL bus. how to use it in software?

Hi, does anyone know how to use a 2nd FSL peripheral attached to microblaze? This is what I did. I have attached 2 peri...

4 18yrs

chrisdekoh

4 18yrs chrisdekoh

UK Embedded Masterclass

A few places left - Embedded Linux Workshop, UML, GUI Development, etc etc.. www.embedded-masterclass.com

0 18yrs

richard

0 18yrs richard

DMA in PLB custom core (XilinxV4)

Hi, I=B4ve problems with my custom IP core with simple DMA capability (Master on PLB). The DMA transfer from the core=B...

0 18yrs

myx2

0 18yrs myx2

Help, router can't rout all connections (XILINX)

I need help. I get this error when I rout my design for my spartan 3: WARNING:Route:438 - The router has detected an un...

6 18yrs

Mark

6 18yrs Mark

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