Field-Programmable Gate Arrays

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Synthesis Comparison

Hello, I am writing my report on a university project. The project work involved an FPGA implementation of a neural net...
4 comments posted 18yrs
posted by obviouslyadummy
4 comments posted 18yrs posted by obviouslyadummy

How to instantiate macro in verilog

Dear all, I've designed a macro, and put "rring r1(.en(en),.ro(ro)); ... to instantiate ring macro, but failed. Any one...
5 comments posted 18yrs
posted by hlyu
5 comments posted 18yrs posted by hlyu

Xilinx DDR2 Interface

I used the latest version of MIG to generate pinouts for a Virtex 4 DDR2 interface. In addition to all the usual Addres...
6 comments posted 18yrs
posted by ben
6 comments posted 18yrs posted by ben

Chipscope is Failing

It works fine for Webpack 10.1 but does not work for Chipscope. I get the following error on chipscope: COMMAND: open_p...
0 comments posted 18yrs
posted by oshea
0 comments posted 18yrs posted by oshea

New to FPGA : Timing Closure

Hi All, I am new to FPGA development , I have encountered a timing closure problem and would appreciate some advice fro...
2 comments posted 18yrs
posted by niladri1979
2 comments posted 18yrs posted by niladri1979

Re: Chip photos of old FPGAs

> I recently found a couple of XC2018 in a drawer. Although > these will probably never see any use again it got me > t...
0 comments posted 18yrs
posted by ehliar-nospam
0 comments posted 18yrs posted by ehliar-nospam

XST design frequency setting

Hey everybody, Just started using Xilinx XST as my synthesis tool and I'm just looking for the command line instruction...
3 comments posted 18yrs
posted by robquigley
3 comments posted 18yrs posted by robquigley

Survey: FPGA PCB layout

Does anybody out there have a good methodology for determining your optimal FPGA pinouts, for making PCB layouts nice,...
93 comments posted 18yrs
posted by dhschetz
93 comments posted 18yrs posted by dhschetz

UK Embedded Masterclass

A few places left - Embedded Linux Workshop, UML, GUI Development, etc etc.. www.embedded-masterclass.com
0 comments posted 18yrs
posted by richard
0 comments posted 18yrs posted by richard

DMA in PLB custom core (XilinxV4)

Hi, I=B4ve problems with my custom IP core with simple DMA capability (Master on PLB). The DMA transfer from the core=B...
0 comments posted 18yrs
posted by myx2
0 comments posted 18yrs posted by myx2

Help, router can't rout all connections (XILINX)

I need help. I get this error when I rout my design for my spartan 3: WARNING:Route:438 - The router has detected an un...
6 comments posted 18yrs
posted by Mark
6 comments posted 18yrs posted by Mark

Wishbone, TSK3000 and endianness problem

Hi all, I'm working on interfacing a custom IP core to a TSK3000 (Altium's P/H:MIPS-like soft processor) over WISHBONE...
0 comments posted 18yrs
posted by nope
0 comments posted 18yrs posted by nope