Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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how do I test signals in a testbench that are 1 or 2 levels down in the UUT?
There has to be a way to do this, right? If I want to test a signal in the UUT, I just have to do this in my testbench: if(txcomstart /= '0') then error
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16 years ago
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Wishbone, TSK3000 and endianness problem
Hi all, I'm working on interfacing a custom IP core to a TSK3000 (Altium's P/H:MIPS-like soft processor) over WISHBONE bus and it seems I've run into some endianness problems. I've always been...
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16 years ago
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ICAP_VIRTEX4 primitive
Hi, I am trying to use the ICAP_VIRTEX4 primitive and I have two questions: 1.- There is very little documentation. I've only found information at th Virtex-4 Libraries Guide for HDL Designs. But then...
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16 years ago
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chipscope pro , lower level signals not visible
I am using xilinx xst to do the synthesis and generate a ngc file . I not using EDK at all. I tried using chipscope pro on the ngc file but it doesnt show me the inner signals. It just shows me the...
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16 years ago
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91c111 drivers for NIOSII without ucosII/lwip stack
hey,everyone! Now ,I have a board with cycloneII70 and a 91c111 ethernet controller,and I want to control the 91c111 including receive packet and send packet and so on ,but I don't want to use the...
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16 years ago
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Virtex 4 DCM problem
Hi all, I'm using a Virtex4 DCM with this configuration shown at the end of the article. I have 100MHz as input and I get as outputs 100MHz,50MHz,25MHz,200MHz. The problem is that sometimes,...
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16 years ago
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Help Need about reconfiguring the PLL with prescale counter n and multiply counter m
Hi, After following the the section titled "Reconfiguring the C0 Counter" gives a step by step description of how to reconfigure the PLL to change the C0 clock output. I get the divided output clock...
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16 years ago
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asic gate count
hi, i have got xilinx fft IP core from coregen. Is there any way that i can get asic gate count for this ? Any help / hint is greatly appreciated. thanks, vijayant.
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16 years ago
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Inconsistent File Reading/writing in binary format using MicroBlaze
---------- Forwarded message ---------- From: Priyantha De Silva Date: Wed, Apr 16, 2008 at 2:26 AM Subject: Inconsistent File Reading/writing in binary format using MicroBlaze To: Shakith Fernando...
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16 years ago
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Snythesis error
Hi, when I synthesize the following, I get warnings. library IEEE; use use ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM;...
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16 years ago
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Pre and Post Synthesis Simulation mismatch
Hey everyone, Im having difficulty with signals that i tie to zero or one (using Verilog 1'b0, 1'b1 etc) appearing as z's in post synthesis simulation. They appear fine in pre synthesis simulation, as...
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16 years ago
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Simulation tools for Xilinx ISE
Howdy - I'm just getting started with FPGAs. In college I remember we used ModelSim with ISE for FPGA simulation. We were able to get a license through our school for free. Like a fool I no longer...
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16 years ago
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Xilinx JTAG Linux programming
Hi all ! i have been installing "" found here and it simply work fine with PCIII I also recommend to read documentation on the web site and inside the source package. Thanks to Uwe ! HTP, habib
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16 years ago
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"Multi-source in Unit" Verilog synthesis woes
Hi everybody, I'm working on a hobbyist board I'm designing to do some audio DSP. I'm a little new to Verilog, although not to programming in general. So far the FPGA design work has been going...
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16 years ago
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DOS script file to synthesize a VHDL design
Does anyone know how can I get started on making a DOS script file to synthesize a VHDL design. I tried understanding something from: But I still need more help. Can someone please tell me the...
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16 years ago
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