Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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how we can prove that really the AES 256 is used to crypt the Bitstream in virtex 5
As my current project is about the security that Xilinx embeds in the Virtex 5 , i have some points that i couldn't understand and really i need help to advance in my project : - first how we can...
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16 years ago
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Very simple VHDL problem
Hi there - I am slowly teaching myself VHDL this weekend. I am getting an error that I do not understand: "parse error, unexpected IF". My very simple code is at the bottom of this post, and the error...
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16 years ago
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Synthesis Comparison
Hello, I am writing my report on a university project. The project work involved an FPGA implementation of a neural network. I have created two versions of the design; a serial and a parallel version....
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16 years ago
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How to instantiate macro in verilog
Dear all, I've designed a macro, and put "rring r1(.en(en),.ro(ro)); ... to instantiate ring macro, but failed. Any one could give some hint? Thank you!
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16 years ago
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Xilinx DDR2 Interface
I used the latest version of MIG to generate pinouts for a Virtex 4 DDR2 interface. In addition to all the usual Address, Data, and Control I/Os, MIG assigned an I/O pin for a signal called...
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16 years ago
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Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff
Hello, I am new to this FPGA stuff and I wanted to purchase a starter kit and get volume pricing for a few Xilinx FPGA's If one where to buy through Avnet or maybe NuHorizons, would anyone like to...
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16 years ago
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Chipscope is Failing
It works fine for Webpack 10.1 but does not work for Chipscope. I get the following error on chipscope: COMMAND: open_platform_usb_cable FREQUENCY=6000000 PORT=USB21 INFO: Started ChipScope host...
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16 years ago
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New to FPGA : Timing Closure
Hi All, I am new to FPGA development , I have encountered a timing closure problem and would appreciate some advice from experienced xilinx guys. My problem is as follows - My system has three major...
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16 years ago
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Re: Chip photos of old FPGAs
Through a couple of web searches I found the following page which I have never seen before: There are a couple of reports related to FPGAs on that page and some for CPLD. The following book was also...
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16 years ago
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XST design frequency setting
Hey everybody, Just started using Xilinx XST as my synthesis tool and I'm just looking for the command line instruction (or GUI) to set the design frequency, I was using precision where it was...
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16 years ago
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Survey: FPGA PCB layout
Does anybody out there have a good methodology for determining your optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? The brute force method is fairly maddening. I'd be curious to...
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16 years ago
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attached a 2nd peripheral to FSL bus. how to use it in software?
Hi, does anyone know how to use a 2nd FSL peripheral attached to microblaze? This is what I did. I have attached 2 peripherals, let's say we call it peripheral1 and peripheral2 to the microblaze's FSL...
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16 years ago
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UK Embedded Masterclass
A few places left - Embedded Linux Workshop, UML, GUI Development, etc etc..
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16 years ago
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DMA in PLB custom core (XilinxV4)
Hi, I=B4ve problems with my custom IP core with simple DMA capability (Master on PLB). The DMA transfer from the core=B4s BRAM (32bit wide) to Memory does not work properly. Every second word is...
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16 years ago
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Help, router can't rout all connections (XILINX)
I need help. I get this error when I rout my design for my spartan 3: WARNING:Route:438 - The router has detected an unroutable situation due to local congestion. The router will finish the rest of...
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16 years ago
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