Field-Programmable Gate Arrays

How to independently program the embedded PowerPC in a Virtex?

Hi, I'm using a Xilinx Virtex-II Pro FPGA on a self-designed PCB and I'd like to ask for a way to program the embedded...

3 comments posted 18yrs

posted by denkedranjoe

3 comments posted 18yrs posted by denkedranjoe

Altera Cyc II config problems

Subject board has two 2C devices and a 3C device in a serial config chain. The 2C device's MSEL pins are jumper configu...

0 comments posted 18yrs

posted by eteam_remove_me

0 comments posted 18yrs posted by eteam_remove_me

Newbie: Testbench question

Hello, I have a question about instantiating a module in a verilog testbench. Sometimes the instantiation may have lots...

8 comments posted 18yrs

posted by jjlindula

8 comments posted 18yrs posted by jjlindula

Turning off the DLL to run DDR2 at very low frequency

Hi, There's been a few discussions about this the last couple years, but it seems nothing ended with firm conclusions....

5 comments posted 18yrs

posted by adubinsky457

5 comments posted 18yrs posted by adubinsky457

opb_intc + PowerPC

Hello. I have a problem with use opb_intc in my projekt In mhs: # External Interrupts PORT IrqSecond_pin = IrqSecond, D...

3 comments posted 18yrs

posted by axalay

3 comments posted 18yrs posted by axalay

not inferred RAM, on QII

Hi, On some pretty obvious piece of VHDL (below) QuartusII does not inferred any RAM !!!!!! (whatever "width" value is....

7 comments posted 18yrs

posted by cupidoREMOVE

7 comments posted 18yrs posted by cupidoREMOVE

DCM configuration in Virtex-4 FPGA

Hi all, I'm having a little problem to implement a DCM. It's the first time i need it (to be able to use DDR SDRAM). Be...

4 comments posted 18yrs

posted by mspiegels

4 comments posted 18yrs posted by mspiegels

Celoxica RC1000

Hi All i am new to FPGA's and have picked up a celoxica rc1000pp (virtex 2000e) cheap, the downside...no manuals or sof...

2 comments posted 18yrs

posted by timpope.programmer

2 comments posted 18yrs posted by timpope.programmer

OPB_MDM functionality

hi, this is my question: Is opb_mdm used to load C code (from executable.elf) from SDRAM?. I have downloaded an aplicat...

0 comments posted 18yrs

posted by pbantunez

0 comments posted 18yrs posted by pbantunez

XmdStub fails when connecting via JTAG.

Hi, I would like to know if anyone has received this message when he tries to start XMD. This message appears some time...

0 comments posted 18yrs

posted by pbantunez

0 comments posted 18yrs posted by pbantunez

ANNOUNCE: Maia 0.8.2: module-level HDL verification tool

Maia is a new tool which automatically creates HDL(*) testbenches from a vector-style description. The trivial test cas...

10 comments posted 18yrs

posted by nospam

10 comments posted 18yrs posted by nospam

Problem writing quadrature decoder

Hi there - I am continuing to attempt to learn VHDL this weekend! Currently I'm trying to interface to the quadrature e...

84 comments posted 18yrs

posted by nleahcim

84 comments posted 18yrs posted by nleahcim

synchronous reset problems on FPGA

Hi, I am wondering if anyone of you have experienced this before. Here goes the reset problem I am facing now. asynchro...

12 comments posted 18yrs

posted by chrisdekoh

12 comments posted 18yrs posted by chrisdekoh

how we can prove that really the AES 256 is used to crypt the Bitstream in virtex 5

As my current project is about the security that Xilinx embeds in the Virtex 5 , i have some points that i couldn't und...

0 comments posted 18yrs

posted by swissiyoussef

0 comments posted 18yrs posted by swissiyoussef

Very simple VHDL problem

Hi there - I am slowly teaching myself VHDL this weekend. I am getting an error that I do not understand: "parse error,...

17 comments posted 18yrs

posted by nleahcim

17 comments posted 18yrs posted by nleahcim