Hey everyone,
Im having difficulty with signals that i tie to zero or one (using Verilog 1'b0, 1'b1 etc) appearing as z's in post synthesis simulation. They appear fine in pre synthesis simulation, as one or zero depending on what i specify, but they always appear as z in post synthesis simulation.
As a result of this i have pre and post synthesis simulation mismatch results and also my bit file doesnt work properly on my fpga (Virtex II).
I'm using XST in ISE 9.2.
Is there a way i can have XST take care of this or must i provide a specific ground signal to a module if i wish to drive a constant zero or one in a circuit? I've inherited some code with *lots* of zero's and one's specified like this and it appeared to work ok in Leonardo Spectrum (our previous synthesis tool).
Any help would be appreciated.
Cheers,
Rob.