Hi all, I'm using a Virtex4 DCM with this configuration shown at the end of the article. I have 100MHz as input and I get as outputs 100MHz,50MHz,25MHz,200MHz.
The problem is that sometimes, apparently random, the DCM doesn't get locked ... but I'm sure that the input is ok, I have to send to or three resets in order to make it lock. I also noticed that if I remove the clock and put it back the DCM looses the locking and doesn't get it again.
I used the same configuration on a Virtex2 and I did not have these problems.
Do you think I'm doing something wrong?
SYSTEM_DCM: DCM generic map ( CLKFX_DIVIDE => 8, CLKFX_MULTIPLY => 2 ) port map ( CLKIN => adc1_clk_in, CLKFB => sys_clock_dcmfb, DSSEN => '0', PSINCDEC => '0', PSEN => '0', PSCLK => '0', RST => my_dcm_reset, CLK0 => sys_clock_dcm, CLKDV => sys_clock_x05_i, CLK2X => sys_clock_x2_i, CLKFX => sys_clock_fx_i, LOCKED => sys_lock );
-- BUFG Instantiation sys_clock_dcm_bufg: BUFG port map( I => sys_clock_dcm, O =>
sys_clock_dcmfb); --100MHz sys_clock_x05_bufg: BUFG port map( I => sys_clock_x05_i, O =>
sys_clock_x05_o); --50MHz sys_clock_fx_bufg : BUFG port map( I => sys_clock_fx_i, O =>
sys_clock_fx_o); --25MHz sys_clock_2x_bufg : BUFG port map( I => sys_clock_x2_i, O =>
ddc_pc_bufg : BUFG port map( I => sys_clock_x05_i, O =>
sys_clock_ddc_pc); ddc_pc_x05_bufg : BUFG port map( I => sys_clock_fx_i, O =>
sys_clock_ddc_pc_x05); ddc_pc_x2_bufg : BUFG port map( I => sys_clock_dcm, O =>