ICAP_VIRTEX4 primitive

Hi, I am trying to use the ICAP_VIRTEX4 primitive and I have two questions:

1.- There is very little documentation. I've only found information at th Virtex-4 Libraries Guide for HDL Designs. But then again, it doesn't sa much about the protocol. Have anybody find more info, or successfull worked with it before? 2.- The manual says I can setup the I/O width to 8, but it doesn't seem t be working.

I am using ISE 9.2 SP3

Any information will be appreciated.

alonzo

-

Message posted using

formatting link
More information at
formatting link

Reply to
rha_x
Loading thread data ...

Try the Xilinx Early Access Partial Reconfiguration Lounge. You have to register for it but it contains a lot more information on the ICAP and PR that the user guide / library guide does.

http://www.xil> Hi,

using

formatting link

Reply to
Erik Anderson

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.