Field-Programmable Gate Arrays

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ICAP_VIRTEX4 primitive

Hi, I am trying to use the ICAP_VIRTEX4 primitive and I have two questions: 1.- There is very little documentation. I'v...
1 comments posted 18yrs
posted by alonzo
1 comments posted 18yrs posted by alonzo

chipscope pro , lower level signals not visible

I am using xilinx xst to do the synthesis and generate a ngc file . I not using EDK at all. I tried using chipscope pro...
1 comments posted 18yrs
posted by nbg2006
1 comments posted 18yrs posted by nbg2006

Virtex 4 DCM problem

Hi all, I'm using a Virtex4 DCM with this configuration shown at the end of the article. I have 100MHz as input and I g...
6 comments posted 18yrs
posted by gnemesis2001
6 comments posted 18yrs posted by gnemesis2001

asic gate count

hi, i have got xilinx fft IP core from coregen. Is there any way that i can get asic gate count for this ? Any help / hi...
9 comments posted 18yrs
posted by vijayant.rutgers
9 comments posted 18yrs posted by vijayant.rutgers

Snythesis error

Hi, when I synthesize the following, I get warnings. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.al...
10 comments posted 18yrs
posted by webmaster
10 comments posted 18yrs posted by webmaster

Pre and Post Synthesis Simulation mismatch

Hey everyone, Im having difficulty with signals that i tie to zero or one (using Verilog 1'b0, 1'b1 etc) appearing as z...
2 comments posted 18yrs
posted by robquigley
2 comments posted 18yrs posted by robquigley

Simulation tools for Xilinx ISE

Howdy - I'm just getting started with FPGAs. In college I remember we used ModelSim with ISE for FPGA simulation. We we...
13 comments posted 18yrs
posted by nleahcim
13 comments posted 18yrs posted by nleahcim

Xilinx JTAG Linux programming

Hi all ! i have been installing "libusb-driver.so" found here http://rmdir.de/~michael/xilinx/ and it simply work fine...
0 comments posted 18yrs
posted by habib
0 comments posted 18yrs posted by habib

"Multi-source in Unit" Verilog synthesis woes

Hi everybody, I'm working on a hobbyist board I'm designing to do some audio DSP. I'm a little new to Verilog, although...
2 comments posted 18yrs
posted by nicholas.clark
2 comments posted 18yrs posted by nicholas.clark

DOS script file to synthesize a VHDL design

Does anyone know how can I get started on making a DOS script file to synthesize a VHDL design. I tried understanding s...
3 comments posted 18yrs
posted by sudhangi
3 comments posted 18yrs posted by sudhangi

Actel Cortex

Hey, Does anybody know if there is a port of Linux on the ARM-Cortex on Actel ? Thanks, John
1 comments posted 18yrs
posted by john
1 comments posted 18yrs posted by john

Which to learn: Verilog vs. VHDL?

Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter Kit with Xilinx ISE. I am an electrical engineer...
44 comments posted 18yrs
posted by nleahcim
44 comments posted 18yrs posted by nleahcim