Latest threads in Field-Programmable Gate Arrays

how do I test signals in a testbench that are 1 or 2 levels down in the UUT?

There has to be a way to do this, right? If I want to test a signal in the UUT, I just have to do this in my testbench:...

7 18yrs

danielgkNOSPAM

7 18yrs danielgkNOSPAM

Wishbone, TSK3000 and endianness problem

Hi all, I'm working on interfacing a custom IP core to a TSK3000 (Altium's P/H:MIPS-like soft processor) over WISHBONE...

0 18yrs

nope

0 18yrs nope

ICAP_VIRTEX4 primitive

Hi, I am trying to use the ICAP_VIRTEX4 primitive and I have two questions: 1.- There is very little documentation. I'v...

1 18yrs

alonzo

1 18yrs alonzo

chipscope pro , lower level signals not visible

I am using xilinx xst to do the synthesis and generate a ngc file . I not using EDK at all. I tried using chipscope pro...

1 18yrs

nbg2006

1 18yrs nbg2006

91c111 drivers for NIOSII without ucosII/lwip stack

hey,everyone! Now ,I have a board with cycloneII70 and a 91c111 ethernet controller,and I want to control the 91c111 in...

0 18yrs

bjzhangwn

0 18yrs bjzhangwn

Virtex 4 DCM problem

Hi all, I'm using a Virtex4 DCM with this configuration shown at the end of the article. I have 100MHz as input and I g...

6 18yrs

gnemesis2001

6 18yrs gnemesis2001

Help Need about reconfiguring the PLL with prescale counter n and multiply counter m

Hi, After following the the section titled "Reconfiguring the C0 Counter" gives a step by step description of how to re...

0 18yrs

ajin1983

0 18yrs ajin1983

asic gate count

hi, i have got xilinx fft IP core from coregen. Is there any way that i can get asic gate count for this ? Any help / hi...

9 18yrs

vijayant.rutgers

9 18yrs vijayant.rutgers

Inconsistent File Reading/writing in binary format using MicroBlaze

---------- Forwarded message ---------- From: Priyantha De Silva Date: Wed, Apr 16, 2008 at 2:26 AM Subject: Inconsiste...

0 18yrs

priyanthads

0 18yrs priyanthads

Snythesis error

Hi, when I synthesize the following, I get warnings. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.al...

10 18yrs

webmaster

10 18yrs webmaster

Pre and Post Synthesis Simulation mismatch

Hey everyone, Im having difficulty with signals that i tie to zero or one (using Verilog 1'b0, 1'b1 etc) appearing as z...

2 18yrs

robquigley

2 18yrs robquigley

Simulation tools for Xilinx ISE

Howdy - I'm just getting started with FPGAs. In college I remember we used ModelSim with ISE for FPGA simulation. We we...

13 18yrs

nleahcim

13 18yrs nleahcim

Xilinx JTAG Linux programming

Hi all ! i have been installing "libusb-driver.so" found here http://rmdir.de/~michael/xilinx/ and it simply work fine...

0 18yrs

habib

0 18yrs habib

"Multi-source in Unit" Verilog synthesis woes

Hi everybody, I'm working on a hobbyist board I'm designing to do some audio DSP. I'm a little new to Verilog, although...

2 18yrs

nicholas.clark

2 18yrs nicholas.clark

DOS script file to synthesize a VHDL design

Does anyone know how can I get started on making a DOS script file to synthesize a VHDL design. I tried understanding s...

3 18yrs

sudhangi

3 18yrs sudhangi

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays