Simulation tools for Xilinx ISE

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The ModelSim starter is limited. I think the main limitation is that it is programmed to get radically slower as the number of lines of HDL increases. -Kevin

I'm aware that there are many free simulators out there - but do any of them interface with ISE like ModelSim does?

Also, I noticed that there is also the ModelSim PE Student Edition. I suspect I still qualify as a student - so maybe that is the best choice?

-Michael

Starter edition slows down to 1% of PE (basically grinds to a halt) after

MXE3 edition operates at 40% of PE and slows down to 1% after 50000 lines.

There is no swift, mixed language or SystemC support in either version.

Hans

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Hi Hans - thanks for the information. I'm not terribly worried about speed at the moment - I'm just trying to learn the basics for now. Do you know how the student edition

Also - is there a Xilinx simulator that is built into ISE? I am following a Xilinx tutorial

Thanks!

-Michael

The most recent version of ISIM (the ISE simulator) is much faster and has a new parser so it supports the language(s) much better. The user interface is a bit coarser and the waveform viewer is not as nice as Modelsim's, but it might work well for you. I didn't consider this because it's not really free, since ISE isn't free, but if you already have ISE it might be a good option. -Kevin

I'm confused - I just downloaded the "ISE WebPACK 9.2i" a couple days ago and didn't pay a thing. (and it never asked me to pay a thing). Does this have a built in simulator, or is it only the version that you pay for that has a built in simulator? Thanks,

-Michael

I believe it is the same speed as PE but I am not 100% sure.

I agree, some companies (I don't want to mention any names

Hans

For behavioral sim you could go with a brand agnostic tool like ghdl and iverilog are both free, and I've used them sucessfully for simple to quite large designs. I find the Xilinx and Altera tools to be too slow and cumbersome, but I haven't compared those sim tools to ghdl or iverilog.

Basically you write your test bench in the same language as a module that uses your hardware module, but does not have to be synthesizable and can use all those extra language pragmas like $monitor(), $fprintf(), $system(), etc. It is also easy to pipe the data into/out of the testbench for external processing and verification. Waveforms can be viewed with gtkwave.

taken from

--------------------------- test.v--------------------------------------------------------------------------------------- module test_fixture; reg clock100 = 0 ; reg latch = 0; reg dec = 0; reg [3:0] in = 4'b0101; wire zero; initial //following block executed only once begin $monitor("%b", u1.value); $dumpfile("count.vcd"); // waveforms in this file.. //$dumpvars; // saves all waveforms #16 latch = 1; // wait 16 ns #10 latch = 0; // wait 10 ns #10 dec = 1; #100 $finish; //finished with simulation end always #5 clock100 = ~clock100; // 10ns clock

// instantiate modules -- call this counter u1 counter u1( .clock(clock100), .in(in), .latch(latch), .dec(dec), .zero(zero)); endmodule /*test_fixture*/

------------------------------------------------------------------------

-------------------- counter.v-------------------------------------------------- /*module************************************

• NAME: counter

• DESCRIPTION:
• downcounter with zero flag and synchronous clear

• NOTES:

• REVISION HISTORY
• Date Programmer Description
• 7/10/97 P. Franzon ece520-specific version

/*======Declarations===============================*/

module counter (clock, in, latch, dec, zero);

/*-----------Inputs--------------------------------*/

input clock; /* clock */ input [3:0] in; /* input initial count */ input latch; /* `latch input' */ input dec; /* decrement */

/*-----------Outputs--------------------------------*/

output zero; /* zero flag */

/*----------------Nets and Registers----------------*/ /*---(See input and output for unexplained variables)---*/

reg [3:0] value; /* current count value */ wire zero;

// Count Flip-flops with input multiplexor always@(posedge clock) begin // begin-end not actually need here as there is only one statement if (latch) value > >> used ModelSim with ISE for FPGA simulation. We were able to get a

I'm not sure if ISIM is in there--check for the executables vlogcomp.exe, vhpcomp.exe, and fuse.exe. (They should be under ise/bin/nt.) -Kevin

----------------------------------------------------- ISE WebPACK 9.2i does not include the HDL simulator. Therefore, you need to install it (ModelSIM XE) separately. There is a WebPack10.1 now, but I haven't check it if it also include the simulator.

chumnarn

al

er

Hi - I do have the three exes Kevin mentioned (vlogcomp.exe, vhpcomp.exe, and fuse.exe) - so I'm assuming that means I have it? Is there a way to quickly test run it?

Thanks,

-Michael

Interesting. Would it be possible to do a functional simulation based on the post-place & route VHDL file generated by ISE with ghdl?