Hi everybody,
I'm working on a hobbyist board I'm designing to do some audio DSP. I'm a little new to Verilog, although not to programming in general. So far the FPGA design work has been going smoothly enough, but I'm having some trouble with synthesizing the code I wrote for my DAC. I tried to avoid all of the 'common' mistakes and design for synthesizability, but there's some I must have missed.
My design simulates just fine, but when I go to synthesize it I get these weird "Multi-source" errors:
ERROR:Xst:528 - Multi-source in Unit on signal
ERROR:Xst:528 - Multi-source in Unit on signal
ERROR:Xst:528 - Multi-source in Unit on signal
ERROR:Xst:528 - Multi-source in Unit on signal
ERROR:Xst:528 - Multi-source in Unit on signal .
I can't find the bug in my design, which means it must be some bug in my own understanding. :)
Any words of insight? My Verilog code follows.
Thanks, Nick
//------------------------------------ code---------------------------------------- module dac_cs4345(CLK, RST_N, SCLK, LRCLK, L_DATA, R_DATA, DATAOUT);
// In this design, CLK = 49.152MHz, MCLK = 24.576MHz, // SCLK = 6.144MHz, LRCLK = 96KHz. They are all in-phase // each other, with the various clocks being generated from // a 49.152MHz crystal and another Veriog module containing // counters.
// Module port declarations
input CLK, RST_N; input SCLK, LRCLK; input [23:0] L_DATA, R_DATA;
output reg DATAOUT;
// Internal declarations
reg r1, r2; wire SCLK_DELAYED;
// Counter used as an index to access data serially. reg [4:0] shift_counter;
// L_Data and R_Data are both registered to protect against // spurious transitions during conversion. reg [23:0] L_DATA_STORAGE; reg [23:0] R_DATA_STORAGE;
// Begin Program
// Since our data is set up on the LRCLK edge, we have to allow // some delay before accessing it. Since SCLK is the clock used // pull data, a slightly delayed SCLK will be generated and used. // SCLK_DELAYED arrives one CLK period after SCLK.
always @(posedge CLK) begin r2