Latest threads in Field-Programmable Gate Arrays

running microblaze from bram through OPB-bus

Hi, We have a design with a microblaze which runs from bram at startup (connected through the LMB bus). After startup i...

4 21yrs

someone

4 21yrs someone

FPGA Configuration Simulation

Hello All, If I am using a Xilinx or any other FPGA and I am not using the platform flash which is recomended to config...

1 21yrs

kedarpapte

1 21yrs kedarpapte

Difference between BUFGDS and IBUFDS on clocks

Dear all, I'm a little bit confused about the usage of IBUFGDS and IBUFDS. In my design (on a XC2V8000 fpga) I have to...

0 21yrs

giachella.g

0 21yrs giachella.g

Linux VHDL Simulator

Hi all, I'm working with ISE 6.3 under Windows right now, I'd like to use it under Linux but I'm holding back because M...

1 21yrs

send_no_spam_to_jimgeorge

1 21yrs send_no_spam_to_jimgeorge

Clock Jitter on Xilinx FPGA

Hi Group, I am using SPARTAN3 CLBs to divide a clock. I can't use the DCM because the input clock is less than the mini...

7 21yrs

Sudhir.Singh

7 21yrs Sudhir.Singh

FPGA Layout question

Hello all, I have a question regarding the layout of a BGA packaged FPGA. For the first time I am using multiple ground...

8 21yrs

jberringer.at

8 21yrs jberringer.at

xilinx embedded MAC

we are using xilinx xc2v3000 (virtex II) FPGA we are trying to do 42 MACs. right now we are doing the multiplication, f...

1 21yrs

wallge

1 21yrs wallge

ADPCM IP core

I am looking for ADPCM IP core Thanks for help

0 21yrs

mariuszb

0 21yrs mariuszb

Interesting article about Xilinx FPGAs in the new Cray

http://www.fpgajournal.com/articles_2005/20050405_cray.htm Leon

3 21yrs

leon_heller

3 21yrs leon_heller

Slow rising strobe used to clock IOB's, can it cause trouble?

Hello, We have a board with multiple IDE interfaces implemented in Virtex2 device. We are using UDMA 3 protocol. One of...

22 21yrs

brijesh_xyz

22 21yrs brijesh_xyz

Major Adresses on Xilinx Virtex-II

Hi, according to the new Virtex-II Platform User Guide the major address of a CLB goes from 4 to n+4 (with n CLB column...

0 21yrs

eem

0 21yrs eem

8 pit PWM generator in one Xilinx Slice !

source is added to "xilcores" project at http://gforge.openchip.org/projects/xilcores/ this mini IP-core is not "done b...

1 21yrs

antti

1 21yrs antti

Sdram controller on the Altera Cyclone board!

Hi I wrote a sdram controller which has pass the RTL simulation. But when it come to the Altera cyclone board,the read/...

1 21yrs

305liuzg

1 21yrs 305liuzg

xilinx appnote 636

Hi, I've been fooling around with the example vhdl for the Xilinx appnote 636 concerning pipelineing a multiplier. The...

0 21yrs

cwoodring

0 21yrs cwoodring

Hey Xilinx

Any chance of there ever being an FPGA where one or more of the SelectRAM blocks is nonvolatile? I design a lot of stuf...

6 21yrs

nospam

6 21yrs nospam

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