Hi, I've been fooling around with the example vhdl for the Xilinx appnote
636 concerning pipelineing a multiplier. The pdf file accompanying the app note is a bit vague on exactly what to do with the example code. I'm having an issue with the ucf file in that if I synthesize the top level wrapper module for the floorplanned multiplier, and then try to P&R it, I get errors in the translate process that claim the wrapped_instantiation instance is not found. This is the sample file: l ibrary ieee; use ieee.std_logic_1164.all;entity SAMPLE_WRAPPER_MULT18X18S_PLUS is port( A_INPUT, B_INPUT:in std_logic_vector(17 downto 0); CLK, RST, CE: in std_logic; P_OUTPUT: out std_logic_vector(35 downto 0)); end SAMPLE_WRAPPER_MULT18X18S_PLUS;
architecture SAMPLE_WRAPPER_MULT18X18S_PLUS_BEHAVIOR of SAMPLE_WRAPPER_MULT18X18S_PLUS is component MULT18X18S_PLUS port( A_INPUT, B_INPUT:in std_logic_vector(17 downto 0); CLK, RST, CE: in std_logic; P_OUTPUT: out std_logic_vector(35 downto 0)); end component;
begin
wrapped_instantiation : MULT18X18S_PLUS port map(A_INPUT => A_INPUT, B_INPUT => B_INPUT, CLK => CLK, RST => RST, CE => CE, P_OUTPUT => P_OUTPUT);
end SAMPLE_WRAPPER_MULT18X18S_PLUS_BEHAVIOR;
When I look at the RTL viewer I see the correct registers and multiplier and it all looks right. There are location constraints in the vhdl for the SAMPLE_WRAPPER_MULT18X18S_PLUS and the pipelined registers are rloc'ed in the ucf file. Well when I ignore the give ucf file and P&R the placement of the pipelined registers is nowhere near what the app note shows.
Here is what NgdBuild prints: Reading NGO file "C:/Xilinx/myprojects/app636/sample_wrapper_mult18x18s_plus.ngc" ... Reading component libraries for design expansion...
Annotating constraints to design from file "SAMPLE_WRAPPER_MULT18X18S_PLUS.ucf" ... ERROR:NgdBuild:753 - Line 1 in 'SAMPLE_WRAPPER_MULT18X18S_PLUS.ucf': Could not find instance(s) 'wrapped_instantiation' in the design. To suppress this error specify the correct instance name or remove the constraint.
and here is what is in the beginnig of the ucf file: ` INST "wrapped_instantiation" RLOC_ORIGIN=X2Y0; INST "wrapped_instantiation/test_mult18x18s" LOC = "MULT18X18_X0Y0";
If I remove the ucf file and do the P&R and then look at the design in the FPGA editor, I see the wrapped_instantiation of the multipllier in the component list.
wrapped_instantiation_a_wire SLICE_X6Y6 SLICE 6 15 wrapped_instantiation_a_wire SLICE_X6Y7 SLICE 6 15 wrapped_instantiation_a_wire SLICE_X6Y8 SLICE 6 15 wrapped_instantiation_a_wire SLICE_X6Y9 SLICE 6 15 wrapped_instantiation_a_wire SLICE_X6Y10 SLICE 6 15 wrapped_instantiation_a_wire SLICE_X6Y11 SLICE 6 15 wrapped_instantiation_a_wire SLICE_X6Y12 SLICE 6 15 wrapped_instantiation_a_wire SLICE_X6Y13 SLICE 6 15 wrapped_instantiation_a_wire SLICE_X5Y13 SLICE 6 15 wrapped_instantiation_b_wire SLICE_X8Y6 SLICE 6 15 wrapped_instantiation_b_wire SLICE_X8Y7 SLICE 6 15 wrapped_instantiation_b_wire SLICE_X8Y8 SLICE 6 15 wrapped_instantiation_b_wire SLICE_X8Y9 SLICE 6 15 wrapped_instantiation_b_wire SLICE_X8Y10 SLICE 6 15 wrapped_instantiation_b_wire SLICE_X8Y11 SLICE 6 15 wrapped_instantiation_b_wire SLICE_X8Y12 SLICE 6 15 wrapped_instantiation_b_wire SLICE_X8Y13 SLICE 6 15 wrapped_instantiation_b_wire SLICE_X5Y12 SLICE 6 15 wrapped_instantiation_test_mult18x18s MULT18X18_X0Y1 MULT18X18 75 15
I am new to the FPGA editor and trying to get a handle on how it can be used. Is this happening because the instantiation is in a behaviorial architecture? I figured since the ucf names the wrapped_instantiation as an INST I could just use the file the way it was and synthesize it?
Any comments appreciated.
Thanks
CTW