source is added to "xilcores" project at
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this mini IP-core is not "done by Antti" so its user contribution and very well done, better documented, can be used in simulations and even uses RLOC to get max density and performance out.
Antti PS the FpgaFreqMeter is also updated and hopefully fixes the problems with jtag chain where FPGA is not last (like the digilent board etc)